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| switi switching ic pef 20450 mtsi pef 20470 mtsi-l pef 24470 mtsi-xl version 1.3 preliminary data sheet, ds 1, nov. 2001 wired communications never stop thinking.
edition 2001-11-20 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2001. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. wired communications p r e l i m i n a r y switi switching ic pef 20450 mtsi pef 20470 mtsi-l pef 24470 mtsi-xl version 1.3 preliminary data sheet, ds 1, nov. 2001 never stop thinking. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com pef 20450 / 20470 / 24470 preliminary revision history: 2001-11-20 ds 1 previous version: pef 20450 / 20470 / 24470 v1.2, preliminary data sheet ds1, 2001-04-04 page content 12 table 5 updated 26 chapter 3.4.3 updated, added figure 9 28 chapter 3.7.1 and chapter 3.7.2 updated 30 chapter 4.2 reworked 49 description of configuration command register 1 and 2 ( cmd1 and cmd2 ) updated 57 description of interrupt status register 1 ( ista1 ) reworked 58 description of interrupt error status register 1 and 2 ( iesta1 and iesta2 ) reworked 60 description of interrupt error mask register 1 and 2 ( intem1 and intem2 ) reworked 74 chapter 6.2 reworked 82 figure 18 updated 85 chapter 6.7.3 reworked 101 chapter 7.1 and table 22 updated 104 table 23 updated 110 table 27 and figure 39 updated 112 added chapter, 7.5?hardware reset timing? 115 table 32 updated. pef 20450 / 20470 / 24470 preliminary data sheet 2001-11-20 table of contents page 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 overview of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 features in detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 standard pbx or co application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 pin diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 local bus interface (pcm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 general purpose port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.3 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.4 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.5 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.6 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 architectural description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 overview of functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 switching factory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 switching modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1.1 minimum and constant delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1.2 subchannel switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1.3 multipoint switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1.4 broadcast switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1.5 bidirectional switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1.6 message mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.2 parallel mode for local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.3 switching block error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.4 analyze connection and data memory . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 clock generator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.1 general overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.2 analog pll (apll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.2.2 jitter transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.3 phase alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.4 pll synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5 loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 read switi configuration with indirect register addressing . . . . . . . . . . 27 3.7 power-on and reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.7.1 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.7.2 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 description of interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 pef 20450 / 20470 / 24470 preliminary data sheet 2001-11-20 table of contents page 4.1 local bus interface (pcm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2 data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.1 intel/siemens or motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.2 de-multiplexed or multiplexed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 general purpose port (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 general purpose clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5.1 frame group outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.5.2 gpclk as clock outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.6 jtag (boundary scan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.6.1 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.6.2 test-access-port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.6.3 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.7 identification code via p read access . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1 register overview for 8-bit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 detailed register description for 8-bit interface . . . . . . . . . . . . . . . . . . . . 42 5.3 register overview for 16-bit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4 detailed register description for 16-bit interface . . . . . . . . . . . . . . . . . . 68 6 programming the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1 read and write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.2 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3 command and register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4 indirect configuration register access . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.5 initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.6 clocking unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.7 local bus (pcm) line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.7.1 standby command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.7.2 determining clock rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.7.3 performing bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.7.3.1 input bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.7.3.2 output bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.8 global clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.8.1 framing groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.9 read time-slot value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.10 establish connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.10.1 establish 8-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.10.2 subchannel switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.10.2.1 establish 4-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.10.2.2 establish 2-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.10.2.3 establish 1-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.10.3 establish broadcast connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 pef 20450 / 20470 / 24470 preliminary data sheet 2001-11-20 table of contents page 6.10.4 establish subchannel broadcast connection . . . . . . . . . . . . . . . . . . . . 94 6.10.5 establish multipoint connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.11 send messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.12 release connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.12.1 release 8-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.12.2 release 4-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.12.3 release 2-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.12.4 release 1-bit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.12.5 release broadcast connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.12.6 release subchannel broadcast connection . . . . . . . . . . . . . . . . . . . . . 99 6.12.7 release multipoint connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.13 stop sending messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.1 pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.2 pcm parallel mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.3 microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.3.1 infineon/intel timing in de-multiplexed mode . . . . . . . . . . . . . . . . . . . 105 7.3.2 infineon/intel timing in multiplexed mode . . . . . . . . . . . . . . . . . . . . . . 106 7.3.3 motorola microprocessor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.4 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.5 hardware reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.3 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.5 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 pef 20450 / 20470 / 24470 list of figures page preliminary data sheet 2001-11-20 figure 1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 standard pbx or co application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5 bidirectional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6 switi clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7 block diagram of apll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8 apll - jitter transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9 example of phase alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10 pcm interface configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11 pcm bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12 multiplexed and in de-multiplexed bus mode . . . . . . . . . . . . . . . . . . . 32 figure 13 gpio port configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 14 frame signal example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 15 order of register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 16 8-bit p access interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 17 16-bit p access interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 18 initialization procedure after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 19 example: input bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 20 example: output bit shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 21 example framing groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 22 example: 8-bit connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 23 subchannel address in time-slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 24 example: 4-bit connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 25 example: 2-bit connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 26 example: 1-bit connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 27 example: broadcast connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 28 example: subchannel broadcast connection . . . . . . . . . . . . . . . . . . . 94 figure 29 example: multipoint connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 30 example: send message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 31 pcm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 32 parallel mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 33 infineon/intel read cycle in de-multiplexed mode . . . . . . . . . . . . . . 106 figure 34 infineon/intel write cycle in de-multiplexed mode . . . . . . . . . . . . . . 106 figure 35 infineon/intel read cycle in multiplexed mode . . . . . . . . . . . . . . . . . 107 figure 36 infineon/intel write cycle in multiplexed mode . . . . . . . . . . . . . . . . . 108 figure 37 motorola read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 38 motorola write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 39 boundary scan timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 40 hardware reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 41 external crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 42 i/o wave form for ac-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 43 outlines of p-mqfp-100-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 pef 20450 / 20470 / 24470 preliminary data sheet 2001-11-20 list of table page table 1 who should read what? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2 switi family tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 3 local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4 gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5 clock pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9 tap controller instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 10 boundary scan idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 11 idcode via p read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 12 register overview for 8-bit interface . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13 value range for spa/dpa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14 value range for itsa/otsa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 15 value range for sca. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 16 register overview for 16-bit interface . . . . . . . . . . . . . . . . . . . . . . . . 67 table 17 affected registers for connection commands . . . . . . . . . . . . . . . . . . 76 table 18 affected registers for configuration commands. . . . . . . . . . . . . . . . . 77 table 19 connection command and parameter codes . . . . . . . . . . . . . . . . . . . 78 table 20 configuration command 1 and parameter codes . . . . . . . . . . . . . . . . 79 table 21 configuration command 2 and parameter code. . . . . . . . . . . . . . . . . 79 table 22 pcm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 23 pcm parallel mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 24 infineon/intel timing in de-multiplexed mode . . . . . . . . . . . . . . . . . . 105 table 25 infineon/intel timing in multiplexed mode . . . . . . . . . . . . . . . . . . . . . 107 table 26 motorola timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 27 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 28 hardware reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 29 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 30 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 31 external capacitances for crystal (recommendation) . . . . . . . . . . . 114 table 32 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 33 input/output capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 pef 20450 / 20470 / 24470 preliminary data sheet 1 2001-11-20 preliminary preface the switching ic (switi) is a family of switching devices for a wide area of telecommunication and data communication applications. this document provides complete reference information according to chip interfaces, programming, internal architecture and applications. organization of this document this preliminary data sheet is divided into 9 chapters. it is organized as follows: ? chapter 1 , overview gives a general description of the product and its family, lists the key features, and presents some typical applications. chapter 2 , pin description lists pin locations with associated signals, categorizes signals according to function, and describes signals. chapter 3 , description of interfaces rough overview of the internal architecture. chapter 4 , description of interfaces short introduction of used interfaces. chapter 5 , register description gives information about all registers accessible via the microprocessor interface according to address, short name, access, reset value and value range. chapter 6 , programming the device gives a variety of examples how to programm the device, lists all available command and parameter values. chapter 7 , timing diagrams contains timing diagrams. chapter 8 , electrical characteristics specification of the electrical parameters. chapter 9 , package outlines outlines of the available packages (p-mqfp-100-2). pef 20450 / 20470 / 24470 preliminary data sheet 2 2001-11-20 preliminary table 1 who should read what? addressed person relevant chapters programmer 3, 5, 6 board designer 2, 3, 4, 7, 8, 9 pef 20450 / 20470 / 24470 overview preliminary data sheet 3 2001-11-20 preliminary 1overview the new switching family, called switi, provides a complete and cost-effective solution for all switching systems. the family is divided in two sub-families, the mtsi family and the htsi family. the preliminary data sheet describes the functionality and characteristic of the mtsi devices. the devices can be used in today ? s switching applications, e.g. conventional pbxs and central offices, as well as in h.100/h.110 applications (only the htsi family), which are the key to high performing cti- and voice-over-ip-applications, one of the most important future technologies in telecommunications. the main requirements of today ? s switching applications are met by the following features: constant delay e.g. to support wide band data switching, or channel bundling bit switching/subchannel switching to support applications such as mobile base stations, dect, computer telephony in addition, the switi family provides new features to ensure a broad range of configurations to make it possible to adapt the device to all switching applications: a compliant h.100/h.110 interface (htsi) 8-channel stream-to-stream switching capability (htsi) message mode, which allows to assign a preset value to any output time-slot gpio (general purpose i/o) port, which is controlled from the external p switi family. the switi family consists of 6 ics with different switching capacities. the possible configurations are shown in table 2 . the htsi versions provide an additional h.100 / h.110 interface, while the mtsis are standard switching devices. all devices can be programmed easily, thus helping the designer/programmer to integrate the device into his application comfortably. table 2 switi family tree name package sales code connec- tions local bus in/out h-bus io htsi-xl (h-mode) p-bga-217-1 pef 24471 htsi-xl 2048 16/16 32 htsi-xl (m-mode) pef 24471 htsi-xl 32/32 - htsi-l (h-mode) p-bga-217-1 pef 20471 htsi-l 1024 16/16 32 htsi-l (m-mode) pef 20471 htsi-l 32/32 - pef 20450 / 20470 / 24470 overview preliminary data sheet 4 2001-11-20 preliminary htsi (h-mode) p-bga-217-1 pef 20451 htsi 512 16/16 32 htsi (m-mode) pef 20451 htsi 32/32 - mtsi-xl p-mqfp-100-2 pef 24470 mtsi-xl 2048 16/16 - mtsi-l p-mqfp-100-2 pef 20470 mtsi-l 1024 16/16 - mtsi p-mqfp-100-2 pef 20450 mtsi 512 16/16 - table 2 switi family tree (cont ? d) name package sales code connec- tions local bus in/out h-bus io p-mqfp-100-2 preliminary data sheet 5 2001-11-20 switching ic switi pef 20450 / 20470 / 24470 version 1.3 cmos type package pef 20450 / 20470 / 24470 p-mqfp-100-2 preliminary 1.1 overview of features general switching capacity of 512, 1024, or up to 2048 connections of different types between different buses programmable data rates of 2.048 mbit/s, 4.096 mbit/s, 8.192 mbit/s, and 16.384 mbit/s on per stream basis 16 pcm highways (in/out) constant delay or minimum delay programmable on per connection basis subchannel switching ability of 1-bit, 2-bit, 4-bit wide time-slots programmable clock shift for local bus automatic data rate adaption optional 8-bit parallel input and/or 8-bit parallel output for first 8 lines of local bus broadcast capabilities multipoint switching ability read and write access to all time-slots message mode (time-slot write access) programmable framing group gpio port 8-bit p-interface supports both intel and motorola mode optional 16-bit p interface mode (instead of gpio port) on chip pll for pcm bus clock operation (master/slave) jtag interface ? boundary scan according to ieee 1149.1 3.3 v power supply 5 v tolerant inputs/outputs pef 20450 / 20470 / 24470 overview preliminary data sheet 6 2001-11-20 preliminary 1.2 features in detail flexible data rates each input and each output line of the local bus is programmable to operate at different data rates. the possible data rates are 2.048 mbit/s, 4.096 mbit/s, 8.192 mbit/s, and 16.384 mbit/s. constant and minimum delay each connection independent of the addressed buses can be determined to be a constant delay or minimum delay connection. constant delay means that any input time- slot or subchannel is available on the programmed output after 2 frames. minimum delay means that the time-slot or subchannel appears at the output as soon as possible. the minimum delay depends on the chosen connections and the possible range is between 0 and 2 frames. subchannel switching each connection can be a 1-bit, 2-bit, 4-bit, or 8-bit connection. subchannel switching has a constant delay of 2 frames. subchannel switching is supported only for data rate of 2.048 mbit/s, 4.096 mbit/s and 8.192 mbit/s. programmable clock shift the position of time-slot 0 of each local bus input line can be programmed within the time-slot before and after the pfs rising edge in half bit steps. also the position of time- slot 0 of all local bus output lines can be programmed within the first time-slot after the pfs rising edge. automatic data rate adaption connections are also possible between lines operating at different data rates. the programmer just specifies input and output line, time-slot, and if necessary, the subchannel. parallel mode the first 8 local bus input and output lines can be configured to one parallel input or output port respectively. in serial mode a time-slot is determined by 8 consecutive data clock cycles according to each line. in parallel mode a time-slot is determined by 1 data clock cycle according to the first 8 lines. pef 20450 / 20470 / 24470 overview preliminary data sheet 7 2001-11-20 preliminary broadcast with this feature it is possible to distribute one incoming time-slot to different output time- slots. multipoint multipoint connections can be seen as the opposite of broadcast connections. here it is possible to generate one output time-slot consisting of several input time-slots. the specified input time-slots are logically and or or connected (selectable) and have a constant delay of 2 frames. read access the programmer has access to any input time-slot. after issuing an appropriate command the arrival of the time-slot will be reported by interrupt. the value can be read from a dedicated register. for every read request the command has to be issued again. message mode (write access) this feature allows a constant value to be sent to any given output time-slot. framing group it is possible to specify up to 8 different framing signals of 8 khz. the position of the rising edge and the pulse width can be programmed for each signal. the reference frame is determined by the pfs signal. the pulse parameters are programmed in half step resolution according to a 16.384 mhz clock. general purpose clocks all 8 gpclk lines can be configured as individual clock outputs with 8 khz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz and for test purposes with the internal frequency or the input frequency of the analog pll (apll). gpio port each line of the general purpose input/output port can be configured to be either input or output. according to an input an edge causes an interrupt. the outputs can be influenced by write access via the microprocessor interface. thus the user has the possibility to observe and influence additional signals for his application. microprocessor interface all devices provide a standard 8-bit microprocessor interface operating in either intel or motorola mode. optionally it is possible to configure the gpio port as additional data lines to provide a 16-bit microprocessor interface. the use of the 16-bit p interface pef 20450 / 20470 / 24470 overview preliminary data sheet 8 2001-11-20 preliminary reduces the number of write cycles required to configure a connection from 7 (in case of 8-bit p interface) to 3 write cycles. input/output tolerance the mtsi can be used in a 5 v environment. inputs and outputs are 3.3 v and 5 v tolerant. the outputs have ttl level driving capability. 1.3 logic symbol the mtsi is a pure pcm switch and provides 16 pcm input lines and 16 pcm output lines. pef 20450 / 20470 / 24470 overview preliminary data sheet 9 2001-11-20 preliminary figure 1 logic symbol mtsi pef 20450/20470/24470 v ss v dd in[15:0] out[15:0] pfs pdc gpio general purpose clocks ds rd wr r/w cs ireq ale mode16 tdi tdo tck tms trst d[7:0] a[4:0] reset misc. switi_035.emf pef 20450 / 20470 / 24470 overview preliminary data sheet 10 2001-11-20 preliminary 1.4 standard pbx or co application the mtsi or the htsi in m-mode can be used, just as the mtsc or mtsl, in standard private branch exchange or central office applications ( figure 2 ), e.g. in the switching network. figure 2 standard pbx or co application line unit epic/ delic switching network coordination processor cp hdlc pcm mtsi/ htsi pbx or co mtsi/ htsi pcm pcm slmd subscriber line modul digital epic/ delic switi_014.emf pef 20450 / 20470 / 24470 pin description preliminary data sheet 11 2001-11-20 preliminary 2 pin description the pin description gives an overview of the pin numbers, names, direction, position and function ordered by the different interfaces. note: all unused input or i/o pins should be connected to v ss to avoid leakage current. 2.1 pin diagrams figure 3 pin configuration mtsi 1 100 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 in12 in13 in14 in15 vdd vss vdd vss out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 vdd vss vdd vss mode16 tdi tdo tms tck vssa vdda vss vdd vss vdd gpclk0 gpclk2 gpclk3 gpclk4 gpclk1 gpclk7 gpclk6 gpclk5 reserved eclki ntwk_2 ntwk_1 pfs pdc ireq/ireq reset cs trst eclko 30 50 51 31 81 80 top view switi_047.emf vss vdd vdd vss a3 a1 d0 ale a0 a4 d1 a2 d2 d3 d4 gpio4 gpio7 gpio6 gpio5 d5 d6 d7 vdd vss gpio0 gpio2 gpio1 gpio3 rd / ds wr / r/w p-mqfp-100-2 pef 20450 / 20470 / 24470 pin description preliminary data sheet 12 2001-11-20 preliminary 2.2 pin definitions and functions 2.2.1 local bus interface (pcm) 2.2.2 general purpose port 2.2.3 clock signals table 3 local bus interface pin no. symbol in (i) out (o) function reset behavior 56 pfs i/o pcm frame synchronization clock of 8 khz high z 57 pdc i/o pcm data clock of 2.048 mbit/s, 4.096 mbit/s, 8.192 mbit/ s, 16.384 mbit/s high z 100-97, 94-83 in[15:0] 1) 1) 100 is in15, 99 is in14, 98 is in13.. i pcm receive data port 15 to 0 31-37, 40-48 out[15:0] 2) 2) 31 is out15, 32 is out14, 33 is out13.. o pcm transmit data port 15 to 0 high z table 4 gpio pin no. symbol in (i) out (o) function reset behavior 28-21 gpio[7:0] 1) d[15:8] 1) 28 is gpio7, 27 is gpio6, 26 is gpio5.. i/o general purpose i/o port (only if 8-bit p interface used) upper 8 bit of 16-bit p interface input table 5 clock pins pin no. symbol in (i) out (o) function reset behavior 69 eclki i external crystal input of 16.384 mhz, or 32.768 mhz external oscillator input of 16.384 mhz, or 32.768 mhz 70 eclko o external crystal output of 16.384 mhz, or 32.768 mhz 73-80 gpclk[7:0] 1) o general purpose clock output (framing signals) high z pef 20450 / 20470 / 24470 pin description preliminary data sheet 13 2001-11-20 preliminary 2.2.4 jtag interface 2.2.5 microprocessor interface 67 ntwk_1 i primary network timing reference input optionally the pll can be synchronized to this input which can be 8 khz, 512 khz, 1.536 mhz, 1.544 mhz, 2.048 mhz 66 ntwk_2 i secondary network timing reference input optionally the pll can be synchronized to this input which can be 8 khz, 512 khz, 1.536 mhz, 1.544 mhz, 2.048 mhz 1) 73 is gpclk7, 74 is gpclk6, 75 is gpclk5.. table 6 jtag interface pin no. symbol in (i) out (o) function reset behavior 51 tck i test clock single rate test data clock. 52 tms i test mode select a ? 0 ? to ? 1 ? transition on this pin is required to step through the tap controller state machine. 55 trst itest reset resets the tap controller state machine (asynchronous reset). 53 tdo o test data out in the appropriate tap controller state test data or a instruction is shifted out via this line. high z 54 tdi i test data input in the appropriate tap controller state test data or a instruction is shifted in via this line. table 7 microprocessor interface pin no. symbol in (i) out (o) function reset behavior 60 cs ichip select active low. a "low" on this line selects all registers for read/ write operations. 3rd ds i read (intel/infineon mode) indicates a read access. data strobe (motorola mode) during a read cycle, ds indicates that the device should place valid data on the bus. during a write access, ds indicates that valid data is on the bus. table 5 clock pins (cont ? d) pin no. symbol in (i) out (o) function reset behavior pef 20450 / 20470 / 24470 pin description preliminary data sheet 14 2001-11-20 preliminary 2.2.6 power supply 4wr r/w i write (intel/infineon mode) indicates a write access. read/write (motorola mode) indicates the direction of the data transfer on the bus. 5 ale i address latch enable controls the on-chip address latch in multiplexed bus mode. while ale is ? high ? , the latch is transparent. the falling edge latches the current address. ale is also evaluated to determine the bus mode (ale fix ? low ? = motorola, fix ? high ? = intel/infineon) 61 mode16 i microprocessor bus 8/16-bit interface selection ( ? low ? = 8 bit, ? high ? = 16 bit) 63 ireq/ ireq o od interrupt request this pin is programmable to push/pull (active high or low) or open-drain. this signal is activated when switi requests an p interrupt. when operated in open drain mode, multiple interrupt sources may be connected. high z 10-6 a[4:0] 1) iaddress bus when operated in address/data multiplex mode, the address pins are externally connected to the d bus. 20-17, 14-11 d[7:0] 2) i/o data bus input 62 reset i system reset switi is forced to go into reset state. 1) 10 is a4, 9 is a3, 8 is a2.. 2) 20 is d7, 19 is d6, 18 is d5.. table 8 power supply pins pin no. symbol in (i) out (o) function 1,15, 29,39, 50,59, 65,81, 95 v dd i power supply 3.3 v 2,16, 30,38, 49,58, 64,82, 96 v ss i digital ground (0 v) 72 v dda i power supply analog logic 3.3 v used for pll 71 v ssa i analog ground (0 v) 68 r reserved. must be connected to ground table 7 microprocessor interface (cont ? d) pin no. symbol in (i) out (o) function reset behavior pef 20450 / 20470 / 24470 architectural description preliminary data sheet 15 2001-11-20 preliminary 3 architectural description the following sections give a short overview of the functionality of the switi. 3.1 functional block diagram figure 4 block diagram output data memory input data memory minimum delay constant delay / subchannel control control control local i/os p-interface pll clocks jtag gpios switching factory i/o block w. autom atic data rate adaption input handler programming line, ts local bus output handler line, ts switi_078.emf pef 20450 / 20470 / 24470 architectural description preliminary data sheet 16 2001-11-20 preliminary 3.2 overview of functional blocks switching factory the switching factory is responsible for transferring and handling the incoming data streams to the assigned output channels and time-slots. the block includes a 512, 1024, or 2048 byte input and output data memory as well as an input and output connection memory. local bus i/o block the block is designed to handle the conversion of the data provided via the switching block and the external local bus (pcm) interface. it performs the pcm timing, the data rate selection and the tristate control. microprocessor interface block a standard 8-bit multiplexed or de-multiplexed p interface is provided, compatible to intel/infineon tech. (e.g. 80386ex, c166) and motorola (e.g. 68040, 68340, 68360, 801) bus systems. if the gpio port is not needed it can be used to provide a 16-bit p interface. gpio block this block supports up to 8 external port lines each one configurable as input or output. a change on an input line may cause an interrupt (if not masked). the user has access to the port configuration and information via the appropriate registers of the p interface. pll and clock block the pll generates all frequencies supporting the local bus (pcm). the internal phase- locked loop (pll) generates all bus frequencies synchronized to a selected reference signal. the output frequency tolerance is equal to the input frequency tolerance. the pll operates from a 16.384 mhz, or 32.768 mhz external crystal, oscillator. pef 20450 / 20470 / 24470 architectural description preliminary data sheet 17 2001-11-20 preliminary 3.3 switching factory as shown in figure 4 the switching factory comprises the input/output data memory and the input/output data handler with the programmed connections. the i/o controller handles all lines operating at the same or different data rate. to establish a connection the user must only program the source line with time-slot and the destination line with the time-slot. the internal controller (data handler) writes the connection in a connection descriptor list and stores this list in the connection data handler. the programming procedure is described in chapter 6 . the incoming time-slot will be stored in the input data memory controlled by the input handler. the output handler controls the constant, minimum delay and subchannel switching. 3.3.1 switching modes the switi family supports a various number of switching modes. all modes are described in the following chapters. 3.3.1.1 minimum and constant delay each connection independent of the addressed buses can be determined to be a constant delay or minimum delay connection. constant delay means that any input time- slot or subchannel is available on the programmed output after 2 frames. minimum delay means that the time-slot appears at the output as soon as possible. the minimum delay depends on the chosen connections and the possible range is between 0 and 2 frames, up to 3 frames in rare cases. an application note which describes the possible connection and minimum delays is available. 3.3.1.2 subchannel switching subchannel switching has a constant delay of 2 frames. every connection can be 1-bit, 2-bit, 4-bit, or normal 8-bit connection. it is possible to combine every kind of subchannel connection, e.g. two 1-bit time-slots with one 4-bit time-slot to one output time-slot. please refer to chapter 6.10.2 for a detailed description about the programming. 3.3.1.3 multipoint switching as described in the overview the multipoint-switching allows to switch several input time- slots to one output time-slot. all input data are logical and or or connected. this mode is selectable with the multipoint connection command. the setup (logical and or or) for the last connection determines all other previous programmed multipoint connections. multipoint switching has always a constant delay. subchannel switching is not supported. pef 20450 / 20470 / 24470 architectural description preliminary data sheet 18 2001-11-20 preliminary 3.3.1.4 broadcast switching broadcast switching allows to distribute one incoming time-slot to different output time- slots. the input and output mechanism is the same as the normal constant delay connection mode with subchannel switching. minimum delay is also supported without subchannel switching. a table with the possible connections and minimum delays will be provided. the broadcast connection is programmed in the same way as a normal connection. the output time-slots can be released with the disconnect part of broadcast command. the last connection must be released with the normal disconnect command. subchannel broadcast it is possible to program one input time-slot as broadcast subchannel connections. that means the bits from the input time-slot are used in several broadcast connections related to one ore more output time-slots. the output time-slots must be released with the disconnect part of broadcast command. the last subchannel connection must be released with the normal disconnect command. (please refer to chapter 6.10.4 for an example) 3.3.1.5 bidirectional switching bidirectional switching allows to install very easily a symmetrical bidirectional connection ( figure 5 ).the input and output mechanism is the same as the normal constant delay or minimum delay connection. the time to program a bidirectional connection is twice as the time to program a normal connection since the internal state machine has to calculate the belonging connection. there is a special command to program a bidirectional connection. a bidirectional connection can only be programmed on an available time-slot and input/output line. pef 20450 / 20470 / 24470 architectural description preliminary data sheet 19 2001-11-20 preliminary figure 5 bidirectional mode 3.3.1.6 message mode the message mode allows to send a predefined 8-bit data value in a defined time-slot on a dedicated destination port. message mode is started or stopped via register ccmd . the data value to be send is predefined in register mv . the time-slot and the destination port is is defined in register otsa and register dpa . 3.3.2 parallel mode for local bus the parallel mode can be set with the ? set parallel mode ? command in the configuration command register. this command set the first 8 input lines and the first 8 output lines of the local bus as parallel bus. if the parallel mode is enabled all included lines will be set to 2.048 mbit/s automatically. if the parallel mode is disabled all lines will keep the data rate of 2.048 mbit/s until a new data rate will be programmed for the selected line. port 0 local bus port 1 local bus port 0 port 1 ts 10 ts 20 swap spa and dpa swap itsa and otsa ts 20 ts 10 port 0 port 1 ts 10 ts 20 spa = 1 itsa = 14 dpa = 0 otsa = a spa = 0 itsa = a dpa = 1 otsa = 14 issued command internal ccmd = 09 switi_067.emf minimum delay pef 20450 / 20470 / 24470 architectural description preliminary data sheet 20 2001-11-20 preliminary the internal s/p-converter is bypassed. the 8 bit data stream per time-slot is distributed on 8 data lines, one bit for every line. the least significant bit is assigned to line 0 and the most significant bit is assigned to line 7. to program a connection line 0 must be used for this special parallel data port. the bit shift value must only be programmed for port 0 and this value will be assigned to the other 7 ports automatically. the initialize sequence is described in chapter 6 . the switching data handling is the same as the data handling for constant delay or minimum delay mode. a timing diagram is provided in the timing diagram chapter ( ? pcm parallel mode timing ? on page 104. ). 3.3.3 switching block error handling the normal procedure to establish a connection is explained in chapter 6 . the way to program a new connection for a specific time-slot and data line is to release the connection and to program the new connection. the switi switching concept provides an internal error handling to detect errors in the switching chain caused by a programming error. a programming error can occur because of noises on the data lines, software errors, etc. a programming error is defined as follows: ? if a non existing connection (minimum, constant delay, or message) will be released. ? or if an existing minimum delay connection will be established. if a programming error or a connection memory overflow is detected the interrupt bit con in the iesta2 register will be set. in this case the last connection which has been tried to establish or to release is not valid. the operation of the switching device is not affected and will be continued without any restrictions. for debug purposes the switi has the capability to write out the content of the complete connection memory and data memory via the microprocessor interface. this procedure is described in chapter 3.3.4 . it is recommended to track all established and connections with the specific customer application software. for debug purpose it is useful to compare the contents of the switching memory with the virtual connections in the application software. 3.3.4 analyze connection and data memory with the special command "memory dump enable" in the connection command register ( ccmd ) it is possible to read the complete memory in a defined sequence from the con register with a 8-bit p access. this feature can be used only for analyze purposes. the command disables the complete switching function as far as all data lines are set to high impedance. if the command is set and after the specific recovery time (200 ns) the connection chain and data memory can be read sequentially by a p access to the con register. the internal controller writes the next 8-bit memory data in the con register if pef 20450 / 20470 / 24470 architectural description preliminary data sheet 21 2001-11-20 preliminary the p read access is finished. that means there is a specific recovery time for the p to the next con read access. the internal memory dump controller reads the present memory contents of the input chain memory, data memory and output chain memory. during the memory dump the internal state machine will loose the synchronization with the external frame structure. therefore a software reset must be issued and the device must be programmed again, except the clock configuration. infineon technologies provides a software driver to recalculate the chain and to recover the current connections. 3.4 clock generator and pll 3.4.1 general overview the following figure gives a overview about the clock generator with the integrated pll. figure 6 switi clock generator the switi clock generator provides all necessary clock signals for the mtsi local bus (pcm) interface. since the device is a pcm clock master capable device there is one digital pll which can be locked to different network reference signals (< 2.048 mhz). switi_058.emf pfs ntwk_1 ntwk_2 eclki eclko apll 2.048mhz frame sm main div norm. operation = 49.152 mhz apll bypass = 16.384/32.768 mhz pdc 2,4,8,16 mhz pfs gpclk[7:0] osc mtsi ref. clock mux pdc div : 1 : 2 : 4 : 8 : 64 : 192 : 193 bypass gpclk[7:0] int. frequency input apll div : 1 : 2 reset = : 1 mux master/slave pcm div 16.384mhz 4.096mhz 2.048mhz 8 khz 8.192mhz 16.384mhz from m ain div div : 8 dpll #1 reset pdc pfs phase alignment programmable pef 20450 / 20470 / 24470 architectural description preliminary data sheet 22 2001-11-20 preliminary the digital pll synchronizes the external crystal or oscillator to the selected reference clock. the digital pll (dpll) will be bypassed if the selected reference signal is >= 2.048 mhz. the input signal for the analog pll (apll) is 2.048 mhz in normal operation mode. the apll is used for multiplying the 2.048 mhz clock into a 49.152 mhz clock and to generate all clock signals for the pcm, and general purpose clock signals. the switi has an on-chip oscillator which allows the user to connect an external 16.384 mhz or 32.768 mhz crystal. instead of using the crystal it is possible to assign a 16.384 mhz, or 32.768 mhz oscillator to the eclki pin. after the power-on or hardware reset the apll is bypassed. the apll will be synchronized (after approximately 750 s) to the external crystal or external oscillator if the command ? set external frequency ? is set. this command must be used otherwise the internal working frequency is equal to the external input frequency and the switi will not work properly. if the apll is locked the status bit ? apll ? in the ista1 register will be set. note: after the reset it is necessary to program the correct crystal or oscillator value as first programming step. otherwise the operation frequency for the switi is not correct. 3.4.2 analog pll (apll) features low cycle-to-cycle jitter < 1 ns natural frequency f g = 15 khz damping factor = 0.7 input frequency = 2.048 mhz in any case output frequency = 49.152 mhz, duty-cycle = 50 % rule behavior = change of output frequency in range of 0 - 10% in response to changes of input frequency phase slope of output frequency equal to phase slope of input frequency note: it is necessary to provide a ?noise free? analog power (v dda /v ssa ) to reduce the internal jitter of the apll. these pins must be decoupled from the digital power (vdd/vss), see also the available application note ?layout notes?. pef 20450 / 20470 / 24470 architectural description preliminary data sheet 23 2001-11-20 preliminary 3.4.2.1 functional description figure 7 block diagram of apll the value of the output frequency depends of the programming of the n-divider. the chosen output frequency for the switi is 49.152 mhz and the input frequency is 2.048 mhz. the macro consists of a digital and an analog pll which are working together. during start-up only the digital one is enabled and makes a coarse adjustment, so that the technology dependency of the circuit is compensated. afterwards the digital pll is disabled again and the analog one is switched on for normal operation. the digital pll is of first order and consists of a frequency detector (fd), an up/down counter, a digital-to-analog converter (dac) and a current controlled oscillator (cco). the fd detects any frequency difference between the reference clock (fref: input clock fin = 2.048 mhz) and the divided oscillator clock. the output signal controls the counter. if the reference frequency is higher than the divided oscillator frequency the counter is increased. the counter output drives a current steering dac which controls the input current of the internal oscillator. its current rises and the output frequency increases until both frequencies are equal. iref up/down counter dac charge pump cco n-divider vtoi frequency detector fin fref fref up/down cw incr decr iprop iint igrob fosc timer locked pu ibias ibias current reference phase/ frequency detector pef 20450 / 20470 / 24470 architectural description preliminary data sheet 24 2001-11-20 preliminary the digital pll is enabled after reset or power up and is disabled after 750 s (lock time of pll). the counter keeps its value and the dac output current irough is constant until the digital pll is reseted. the second order analog pll consists of a phase/frequency detector (pfd), a charge pump (cp), a loop filter and the cco. the pfd which is sensitive to the rising edge detects any phase or frequency difference between the input clock (fref ) and the divided output clock (feedback ) and generates a control signal proportional to the phase difference. the output signals up and down cause the charge pump to modulate the amount of charge in the low pass filter (vtoi) for the integral part (iint ) and to feed current into the cco for the proportional part (iprop ). with these two currents and the dac output irough the cco is controlled. if feedback is leading fref , the oscillator is too fast. the down signal is activated and the cp subtracts some current ipro p. when fref is in phase with the feedback the pll will hold the control current at that level and phase lock will be achieved. thus through this negative feedback arrangement, the pll causes the feedback and fref signals to be equal with minimum phase offset. if the analog pll becomes unstable, a signal pllko is generated which resets the digital pll. pef 20450 / 20470 / 24470 architectural description preliminary data sheet 25 2001-11-20 preliminary 3.4.2.2 jitter transfer function jitter transfers or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. figure 8 shows the jitter transfer function of the switi device. the cutoff frequency of the integrated low pass filter is f g =15khz. figure 8 apll - jitter transfer function 0,1 0,2 0,3 0,4 1 234 10 0 +2 +4 +6 +8 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 f/f g 20lg |h(f)| pef 20450 / 20470 / 24470 architectural description preliminary data sheet 26 2001-11-20 preliminary 3.4.3 phase alignment if the phase alignment function is enabled all pll output signal and the main divider are edge synchronized with the pll clock input. if the selected reference signal is less than 2.048 mhz the edge synchronization resolution depends on the selected external crystal/oscillator frequency. if the phase alignment function is disabled the pll output frequency (49.152 mhz) is edge synchronized with the pll input frequency and the main divider output frequencies are edge synchronized with pll output frequency. an example of phase alignment functionality is shown in figure 9 . phase alignment is required to keep the output signals in phase relative to the input signals. after reset phase alignment is automatically activated in slave mode and turned off in master mode. note: the phase alignment should be disabled for all reference frequencies <2.048mhz. figure 9 example of phase alignment apll output (49.152 mhz) main divider output apll input (2.048 m hz) phase difference phase alignment enabled phase alignment disabled apll output (49.152 mhz) main divider output apll input (2.048 m hz) switi_091.emf pef 20450 / 20470 / 24470 architectural description preliminary data sheet 27 2001-11-20 preliminary 3.4.4 pll synchronization the pll reference source can be selected from the primary reference master source (pfs, pdc, ntwk_1/_2). if the selected reference signal is less than 2.048 mhz the main digital pll is used to synchronize the analog pll. the digital pll is sourced from the external oscillator, or crystal. in this case the analog pll output frequency tolerance is equal to the external oscillator/crystal frequency tolerance. furthermore the analog pll can be sourced directly from the external oscillator, or crystal, or from the pdc input. all generated output frequencies will have the same tolerance as the selected input frequency. 3.5 loops the loop command in the configuration command register cmd2 provides support for automatic pcm-pcm loops. all input lines are pad connected with the corresponding output line. after the loop disable command was set the lines will be set in high-impedance after approximately two frames. 3.6 read switi configuration with indirect register addressing since the switi configuration can be programmed with defined instructions in the cmd1 and cmd2 registers it is possible to read the current configuration through the indirect access registers. the indirect addressing is started by writing one of the five read configuration commands in the cmd2 register. the five commands can be separated in two groups, internal configuration and external line configuration. the internal configuration, e.g. clock generator, ireq pin can be read with the command "read configuration". the internal settings are decoded with the instruction bits i3..0. the data rate for the pcm interface can be read with the "read local bus (pcm) line configuration" command. the "read gpclk configuration" and "read bit/clock shift configuration" must be issued to get the gpclk line configuration and the bit shift value. the tsv and con registers contain the required information after the internal read process is complete. the recovery time is 240 ns. to read the correct configuration data from the tsv register it is not allowed to use the command "read time-slot value" before the tsv register has been read. pef 20450 / 20470 / 24470 architectural description preliminary data sheet 28 2001-11-20 preliminary 3.7 power-on and reset behavior 3.7.1 hardware reset there are two independent low active reset pins: reset and trst . if the reset pin is activated, it immediately sets all outputs and i/o ports into tri-state, except the eclko pin. after the reset process the correct external frequency must be set with the command ? set external frequency ? accordingly. this command starts the configuration process for the apll. the apll is locked after 750 s. during this period the apll is bypassed and the internal frequency is 2.048 mhz. if the apll is locked the internal frequency will be 49.152 mhz. individual output sections must be enabled by setting the command in the configuration command register cmd1 , or cmd2 . internally all state machines, counters and registers are cleared and set to their defined reset value. the reset pin doesn ? t control the boundary scan register and tap-controller. if the trst pin is asserted the tap-controller will go into the test-logic-reset state and all boundary scan elements are bypassed. all outputs and i/o-pins are controlled by the core logic and are tristated according to the programmed functionality or the core reset condition (pin reset ). the hardware reset must be issued for a minimum of 1 s, for more details please refer to the chapter ? hardware reset timing ? on page 112. 3.7.2 software reset the software reset is accomplished by setting the ? set software reset ? command in the cmd2 register. the software reset clears the complete device except the clocking unit and the temporary microprocessor registers (e.g. cmd1 ). the software reset can be deactivated with the ? set software reset ? command. during the software reset the microprocessor interface doesn ? t accept any other commands for a minimum of 1 s. pef 20450 / 20470 / 24470 description of interfaces preliminary data sheet 29 2001-11-20 preliminary 4 description of interfaces 4.1 local bus interface (pcm) the local bus is a pcm interface consisting of input and output data lines (in, out), a pcm data clock pdc and a frame synchronization signal pfs. figure 10 pcm interface configurations the pfs frame sync is a 8 khz signal and delimiting the frame. this input signal is used by the switi to determine the start of a frame. a frame is divided into 8-bit wide time-slots. the amount of time-slots within a frame depends on the selected data rate of pdc which can be 2.048 mbit/s, 4.096 mbit/s, 8.192 mbit/s, 16.384 mbit/s. the pfs input has a schmitt-trigger characteristic. the pdc data clock input supplies the switi with a data clock. it can be operated with 2.048 mhz, 4.096 mhz, 8.192 mhz, or 16.384 mhz data rate clock depending on the selected highest data mode. the pdc clock signal must be equal or higher as the highest data rate. the pdc input has a schmitt-trigger characteristic. a clock slave must receive pfs and pdc whereas a clock master drives these signals. to enable or disable the signals for the clock master the command ? pcm clock input/ output selection ? must be issued. the time-slots are transmitted and received via 16 input and 16 output lines ( in[15:0] , out[15:0] ) . the input lines have a schmitt-trigger characteristic. the output lines have tristate outputs with push-pull characteristic. for every time-slot not participating to a connection the output is high impedance. with the special command "local bus (pcm) standby" in the cmd2 register it is possible to set all pcm lines in a high impedance state during the normal operation mode. all pcm lines are in high impedance state after the reset process and must be enabled with the "local bus (pcm) standby" command. all lines which are not participating on a switching operation are in high impedance state and the time-slot information on the input lines are discarded automatically. pcm i/o pfs pdc in out pcm i/o pfs pdc in out clock slave clock master switi_037.emf pef 20450 / 20470 / 24470 description of interfaces preliminary data sheet 30 2001-11-20 preliminary figure 11 pcm bit shifting for each pcm input line the offset of time-slot zero can be adjusted in a range from 0 to 7 bit in half clock resolution before or after the pfs rising edge. for all output lines the offset of time-slot zero can be adjusted in a range from 0 to 7 bit in half clock resolution after the pfs rising edge. the resolution depends on the selected data rate that means the resolution doesn ? t depend on the pdc signal. after the reset process the bit shift is disabled for all lines. that means the time-slot 0 starts with the rising edge of pfs. all input data will be sampled with falling edge of the selected data rate and the output data are valid with the rising edge of the selected data rate. 4.2 data rate the mtsi provides the programming of different data rates for all data lines. all local bus lines can operate with 2.048 mhz, 4.096 mhz, 8.192 mhz, and 16.384 mhz having data rates of 2.048 mbit/s, 4.096 mbit/s, 8.192 mbit/s and 16.384 mbit/s. the input and output lines are independent of each other, i.e. for a given bus line the input and the output lines can be programmed with different data rates. the maximum aggregate data rate supported at the input and output bus lines is 262.144 mbit/s, with all lines operating at 16.384 mbit/s (i.e. 16 lines x 16.384 mbit/ s per line = 262.144 mbit/s, as input and/or output). pfs 01 0 77 data rate of selected line input 0 offset of ts0 input 1 offset of ts0 outputs offset of ts0 switi_039.emf pef 20450 / 20470 / 24470 description of interfaces preliminary data sheet 31 2001-11-20 preliminary 4.3 microprocessor interface a standard 8-bit multiplexed or non-multiplexed p interface is provided. it is compatible to intel/siemens (e.g. 80386ex, c166) or motorola (e.g. 68040, 68340, 68360, 801) bus systems. if the gpio port is not needed it can be used to provide a 16-bit p interface. the 16-bit mode is determined according to mode16 input pin. mode16 = ? 0 ? -> 8-bit interface mode16 = ? 1 ? -> 16-bit interface this chapter describes how to configure the p interface to each mode. 4.3.1 intel/siemens or motorola mode the intel/siemens or motorola mode for the p interface can be configured during the hardware reset process in conjunction with the ale pin. ? ale permanently driven to ? low ? => motorola mode ? ale permanently driven to ? high ? => intel/siemens mode ? edge on ale => intel/siemens multiplexed mode a falling or rising edge on ale during the normal operation selects the multiplexed mode immediately. with the hardware reset and the tied ale pin it is possible to return to the motorola or intel/siemens mode. 4.3.2 de-multiplexed or multiplexed mode in both modes, the a-bus and the d-bus are used in parallel. the a-bus should be connected to the lsbs of ad-bus, coming from the p, also in multiplexed mode. the next figure describes the connection to the address and data buses in the different modes. note: motorola mode is used only with de-multiplexed ad bus. intel/siemens mode may be used with both, multiplexed or de-multiplexed ad bus. pef 20450 / 20470 / 24470 description of interfaces preliminary data sheet 32 2001-11-20 preliminary figure 12 multiplexed and in de-multiplexed bus mode note: in both modes only the 5 lsbs of a-bus or ad/bus are connected to the address inputs. multiplexed mode p switi ad d a ale ale latch de-multiplexed mode p switi d d a ale latch ?1? a 8/16 5 8/16 5 pef 20450 / 20470 / 24470 description of interfaces preliminary data sheet 33 2001-11-20 preliminary 4.4 general purpose port (gpio) this port consists of 8 lines each one configurable as input or output. a change on an input line may cause an interrupt (if not masked). the user has access to the port configuration and information via the appropriate registers of the p interface. figure 13 shows an example. figure 13 gpio port configuration example 4.5 general purpose clocks the switi provides 8 general purpose clock lines. with two independent commands in the cmd2 register the lines can be configured as frame group signals or individual clock signals. the last written command for a line is valid and controls the multiplexer. 1 0 1 0 x x x x x x x x 1 1 0 0 1 1 1 1 0 0 0 0 70 1 changes in line 1 or line 0 cause interrupts gpio pin no. signal 1 0 1 0 1 1 1 x x x x 0 0 1 0 x x x x 1 1 0 1 x = don't care contains current value of input lines change on input line 1 detected line 7 to 4 as outputs line 3 to 0 as inputs switi_055.emf 2 3 4 5 6 gpio output register gpio mask register gpio direction register gpio input register gpio interrupt register drive 1010 on lines [7:4] 1->0 pef 20450 / 20470 / 24470 description of interfaces preliminary data sheet 34 2001-11-20 preliminary 4.5.1 frame group outputs via 8 output lines it is possible to provide 8 different framing signals which are used for synchronization purpose. all signals have a period of 125 s. their offset can be programmed individually within the pfs determined frame in a resolution of 61 ns (i.e. 1/16.384 mhz). the default start point for the offset is the beginning of a frame (rising edge of pfs and the clock signal). the start point for the offset can be shifted for an half clock cycle, that means the second start point is determined with the rising edge of pfs and the next falling edge of the clock signal (as shown in figure 14 ). the high time of the signal can also be programmed in steps of 61 ns. all frame signals can be controlled as high or low active. figure 14 frame signal example figure 14 shows an example of a frame signal beginning with the rising edge of the 64th clock cycle with a length of 4 clock cycles. further programming examples can be found in chapter 6.8.1 . 4.5.2 gpclk as clock outputs all 8 gpclk lines can be configured as individual clock outputs with 8 khz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz and for test purposes with the internal frequency or the input frequency of the analog pll (apll). all clock signals are generated from the analog pll output frequency which is the internal frequency. the quality of all output frequency signals depends on the quality of the selected input pll frequency. pfs 125s 16.384 mbit/s 01 frame signal 125s 64 switi_038.emf pef 20450 / 20470 / 24470 description of interfaces preliminary data sheet 35 2001-11-20 preliminary 4.6 jtag (boundary scan) the switi provides a fully ieee 1149.1 compatible boundary scan support consisting of: ? a complete boundary scan chain ? a test access port controller (tap controller) ? five dedicated pins: tck, tms, tdi, tdo and a trst to asynchronously reset the tap controller ? one 32-bit idcode register 4.6.1 boundary scan all pins except power supply and crystal are included in the boundary scan. depending on the pin functionality one (input), two (output, enable) or three (input, output, enable) boundary scan cells are provided. the maximum clock rate at pin tck is 10 mhz. 4.6.2 test-access-port (tap) the following signal pins allow the boundary scan test logic to be accessed: ? tck ? test clock input to which a central bsc test clock is applied. this bsc test clock is independent of the system clock. clock phases are derived from this clock for test sequence control. ? tms ? test mode select control input for which the desired status changes at the tap controller by applying a certain level (0/1) caused by the rising edge of tck. ? tdi ? test data input whose data is inserted into the test logic with the rising edge of the tck. ? tdo ? test data output with tristate capability which is only active during the shift-ir and shift-dr controller state, and whose data is driven with the falling edge of tck. pef 20450 / 20470 / 24470 description of interfaces preliminary data sheet 36 2001-11-20 preliminary 4.6.3 tap controller the test access port (tap) controller implements the state machine defined in the jtag standard ieee 1149.1. transitions on the pin tms cause the tap controller to perform a state change. the possible instructions are listed in the following table. the instruction length is four bit. extest is used to verify the board interconnections. when the tap controller is in the state ? update dr ? , all output pins are updated with the falling edge of tck. when it has entered state ? capture dr ? the levels of all input pins are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. intest supports internal chip testing. when the tap controller is in the state ? update dr ? , all inputs are updated internally with the falling edge of tck. when it has entered state ? capture dr ? the levels of all outputs are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. sample/preload the sample/preload instruction enables all signal pins (inputs and outputs) to be sampled during operation (sample) and the result to be shifted out through the shift bsc register. the function of the internal logic is not influenced by this instruction. while shifting out, the bsc cells can be serially loaded at the same time with defined values through tdi (preload). the sample/preload instruction selects the boundary scan register in normal mode. in state capture-dr data is loaded into the boundary scan register with the rising edge of tck. in state update-dr the contents of the boundary scan register are written into the second register stage of the boundary scan table 9 tap controller instructions code instruction function 0000 extest external testing 0001 idcode reading id code 0100 highz high impedance state of all boundary scan outputs 0101 sample/preload snap-shot testing 0110 intest internal testing 0111 clamp reading outputs 1111 bypass bypass operation pef 20450 / 20470 / 24470 description of interfaces preliminary data sheet 37 2001-11-20 preliminary register. this data become effective at the outputs only if an instruction has been activated that sets the bsc register to test mode: e.g. extest or clamp. idcode the 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to ? 1 ? .. clamp the bsc register is in test mode. for the duration of the clamp instruction, the bypass register is selected so that a minimal shift path is created. during shift-dr data can be shifted through the bypass register. the contents of the bsc register does not change during the update-dr state. highz the highz instruction disables all outputs if switched to high impedance state. the outputs are switched to high impedance in state update-ir. the outputs are redefined according to the next new instruction if another instruction has become active with update-ir. the selected test data register is the bypass register. bypass a bit entering tdi is shifted to tdo after one tck clock cycle, e.g. to skip testing of selected ics on a printed circuit board. version device code manufacturer code output xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx 1 --> tdo table 10 boundary scan idcode version device code manufacture code bit0 mtsi 0010 0000 0000 0110 1001 0000 1000 001 1 mtsi-l 0010 0000 0000 0110 1010 0000 1000 001 1 mtsi-xl 0010 0000 0000 0110 1011 0000 1000 001 1 pef 20450 / 20470 / 24470 description of interfaces preliminary data sheet 38 2001-11-20 preliminary 4.7 identification code via p read access the switi offers two possibilities to read the identification code. ? via the jtag port as described in chapter 4.6 ? or via the processor interface after a hardware reset the identification code is stored in the general purpose interrupt register ( gpi ) and can be read via the processor interface. the high nibble is the version number and the low nibble is equal to the low nibble of the device code shown in table 11 . for the 8-bit p interface configuration the first write access to the general purpose mask register ( gpm ) will reset the register gpi to 00 h . if the p interface is configured as a 16-bit interface the idcode can always be read from the gpi register, that means the gpi register will not be reset. the idcode for the p read access is shown in table 11 . note: the version number of the idcode register remains unchanged. table 11 idcode via p read access 8-bit idcode (msb..lsb) version device code mtsi 0010 1001 mtsi-l 0010 1010 mtsi-xl 0010 1011 pef 20450 / 20470 / 24470 register description preliminary data sheet 39 2001-11-20 preliminary 5 register description the register description gives information about all registers accessible via the microprocessor interface according to address, short name, access, reset value and value range. pef 20450 / 20470 / 24470 register description preliminary data sheet 40 2001-11-20 preliminary 5.1 register overview for 8-bit interface table 12 register overview for 8-bit interface reg name access 8-bit address reset value comment page no. spa rd/wr 00 h 00 h source port address register value range see table 13 42 itsa rd/wr 01 h 00 h input time-slot address register value range see table 14 42 dpa rd/wr 02 h 00 h destination port address register value range see table 13 42 otsa rd/wr 03 h 00 h output time-slot address register value range see table 14 43 sca rd/wr 07 h 00 h subchannel address register value range see table 15 43 gi1 rd/wr 04 h 00 h general input register 1 44 gi2 rd/wr 05 h 00 h general input register 2 46 ccmd rd/wr 06 h 00 h connection command register 47 cmd1 rd/wr 08 h 00 h configuration command register 1 49 cmd2 rd/wr 0a h 00 h configuration command register 2 52 mv rd/wr 0c h 00 h message value register 56 ista1 rd 0e h 00 h interrupt status register 1 57 iesta1 rd 10 h 00 h interrupt error status register 1 58 iesta2 rd 11 h 00 h interrupt error status register 2 58 intm1 rd/wr 12 h 3d h interrupt mask register 1 59 intem1 rd/wr 14 h 3f h interrupt error mask register 1 60 intem2 rd/wr 15 h ff h interrupt error mask register 2 60 gppi rd 16 h 00 h general purpose port input register 61 gppo wr 18 h 00 h general purpose port output register 61 gpd rd/wr 1a h 00 h general purpose direction register 61 gpm rd/wr 1b h ff h general purpose mask register 62 gpi rd 1c h idcode general purpose interrupt register 62 tsv rd 1e h xx h time-slot value register 63 con rd 1f h xx h configuration register 66 pef 20450 / 20470 / 24470 register description preliminary data sheet 41 2001-11-20 preliminary table 13 value range for spa/dpa addressed lines value range bit3..0 local bus input lines 15..0 table 14 value range for itsa/otsa data rate number of available time-slots (bit7..0) 2.048 mbit/s 31..0 4.096 mbit/s 63..0 8.192 mbit/s 127..0 16.384 mbit/s 255..0 table 15 value range for sca mode range 1-bit switching 0..7 for isca0..2; 0..7 for osca0..2 2-bit switching 0..3 for isca0..1; 0..3 for osca0..1 4-bit switching 0..1 for isca0; 0..1 for osca0 pef 20450 / 20470 / 24470 register description preliminary data sheet 42 2001-11-20 preliminary 5.2 detailed register description for 8-bit interface source port address register rd/wr address: 00 h reset value: 00h input time-slot address register rd/wr address: 01 h reset value: 00h destination port address register rd/wr address: 02 h reset value: 00h 76543210 spa 0 0 0 0 pa3 pa2 pa1 pa0 bit7..4 must be set to 0 pa3..0 port address 76543210 itsa tsa7 tsa6 tsa5 tsa4 tsa3 tsa2 tsa1 tsa0 tsa7..0 time-slot address 76543210 dpa 0 0 0 0 pa3 pa2 pa1 pa0 bit7..4 must be set to 0 pa3..0 port address pef 20450 / 20470 / 24470 register description preliminary data sheet 43 2001-11-20 preliminary output time-slot address register rd/wr address: 03 h reset value: 00h subchannel address register rd/wr address: 07 h reset value: 00h 76543210 otsa tsa7 tsa6 tsa5 tsa4 tsa3 tsa2 tsa1 tsa0 tsa7..0 time-slot address 76543210 sca 0 0 osca2 osca1 osca0 isca2 isca1 isca0 osca2..0 output subchannel address isca2..0 input subchannel address pef 20450 / 20470 / 24470 register description preliminary data sheet 44 2001-11-20 preliminary general input register 1 rd/wr address: 04 h reset value: 00h in case of a pll reference selection command (cmd1) the content of this register is interpreted as follows: in case of a bit shift command (cmd1) the content of this register is interpreted as follows: 76543210 gi1 gv7 gv6 gv5 gv4 gv3 gv2 gv1 gv0 gv7..0 general value gv2..0 clock frequency 000 = 8 khz 001 = 512 khz 010 = 1.536 mhz 011 = 1.544 mhz 100 = 2.048 mhz 101 = 4.096 mhz 110 = 8.192 mhz 111 = 16.384 mhz gv4 bit shift value (only for input lines) 0 = bit shift applies before pfs rising edge 1 = bit shift applies after pfs rising edge gv3..1 bit shift value (range: 7 to 0) gv0 edge control bit (half clock shift) 0 = data transmit with rising edge and is sampled with falling edge 1 = data transmit with falling edge and is sampled with rising edge pef 20450 / 20470 / 24470 register description preliminary data sheet 45 2001-11-20 preliminary in case of the gpclk as frame signal command (cmd2) the content of this register is interpreted as follows: in case of the gpclk as clock signal command (cmd2) the content of this register is interpreted as follows: gv7..2 offset within the pfs frame in number of 16.384 mhz clock cycles (lower 6 bits; refer to gi2 for the upper part) gv1 edge control bit 0 = data changes with rising edge and is sampled with falling edge 1 = data changes with falling edge and is sampled with rising edge gv0 not used gv2..0 output frequency for the selected line 000 = 8 khz 001 = 2.048 mhz 010 = 4.096 mhz 011 = 8.192 mhz 100 = 16.384 mhz 101 = input analog pll (2.048 mhz) 110 = internal frequency (49.152 mhz) pef 20450 / 20470 / 24470 register description preliminary data sheet 46 2001-11-20 preliminary general input register 2 rd/wr address: 05 h reset value: 00h in case of the gpclk as frame signal command (cmd2) the content of this register is interpreted as follows: 76543210 gi2 gv7 gv6 gv5 gv4 gv3 gv2 gv1 gv0 gv7..0 general value gv7..5 width of the pulse in number of 16.384 mhz clock cycles from 1 to 8 i.e. gv7..5 = 000 => 1 clock cycle, gv7..5 = 010 => 3 clock cycles gv4..0 offset within the pfs frame in number of 16.384 mhz clock cycles (upper 5 bits; refer to gi1 for the lower part) pef 20450 / 20470 / 24470 register description preliminary data sheet 47 2001-11-20 preliminary connection command register rd/wr address: 06 h reset value: 00 h 76543210 ccmd i3 i2 i1 i0 cc3 cc2 cc1 cc0 cc3..0 command code 0000 = no operation at all 0001 = constant delay connection command (incl. broadcast connection) (spa, itsa, dpa, otsa, sca are considered) i1..0 subchannel mode 00 = 8-bit wide time-slots 01 = 4-bit wide time-slots 10 = 2-bit wide time-slots 11 = 1-bit wide time-slots 0010 = minimum delay connection command (incl. broadcast connection) (spa, itsa, dpa, otsa are considered) 0011 = send message command (always constant delay) (dpa, otsa, mv are considered) 0100 = stop message command (dpa, otsa are considered) 0101 = disconnect command (spa, itsa, dpa, otsa, sca are considered) i1..0 see i1..0 of constant delay connection command (incl. broadcast connection) 0110 = disconnect part of broadcast command (spa, itsa, dpa, otsa, sca are considered) i1..0 see i1..0 of constant delay connection command (incl. broadcast connection) 0111 = multipoint connect command (spa, itsa, dpa, otsa are considered) i0 multipoint mode 0 = logical or connection 1 = logical and connection pef 20450 / 20470 / 24470 register description preliminary data sheet 48 2001-11-20 preliminary 1000 = disconnect all command 1001 = bidirectional connect command (spa, itsa, dpa, otsa are considered) i0 delay mode 0 = minimum delay 1 = constant delay 1010 = memory dump (connection and data memory) i0 memory dump 0 = disable 1 = enable pef 20450 / 20470 / 24470 register description preliminary data sheet 49 2001-11-20 preliminary configuration command register 1 rd/wr address: 08 h reset value: 00h 76543210 cmd1 i3 i2 i1 i0 cc3 cc2 cc1 cc0 cc3..0 command code 0000 = no operation 0001 = not used 0010 = pll reference selection command (gi1 is considered to set the frequency) i3..0 synchronization information 0000 = no synchronization = internal oscillator (default) 0001 = synchronizes the pll to pfs 0010 = synchronizes the pll to pdc 0011 = not used 0100 = not used 0101 = synchronizes the pll to ntwk_1 0110 = synchronizes the pll to ntwk_2 0011 = start special configuration command i3..0 only one code is allowed 1111 = start special configuration register programming 0100 = write special configuration command i3..0 only one code is allowed 1111 = write special configuration register (gi1 is considered) 0101 = not used 0110 = pcm clock input/output selection command (default: pfs and pdc inactive) i2..0 frequency information 000 = not used 001 = enable pfs and pdc = 2.048 mhz 010 = enable pfs and pdc = 4.096 mhz 011 = enable pfs and pdc = 8.192 mhz pef 20450 / 20470 / 24470 register description preliminary data sheet 50 2001-11-20 preliminary 100 = enable pfs and pdc = 16.384 mhz i3 direction information 0 = pfs and pdc as input 1 = pfs and pdc as output 0111 = not used 1000 = not used 1001 = not used 1010 = phase alignment i2..0 must be set to 000 i3 pll phase alignment (please see description, chapter 3.4.3 ) 0 = disable (default after reset) 1 = enable the pll phase alignment must be disabled for reference frequencies < 2.048 mhz 1011 = set bit rate command local bus (pcm) (default for all lines = 2.048 mbit/s) i1..0 base bit rate information 00 = 2.048 mbit/s 01 = 4.096 mbit/s 10 = 8.192 mbit/s 11 = 16.384 mbit/s i2 destination information 0 = no effect 1 = set rate of input lines (spa is considered) i3 destination information 0 = no effect 1 = set rate of output lines (dpa is considered) 1100 = not used 1101 = read time-slot command i0 destination information 0 = read input time-slots (spa, itsa are considered) 1 = read output time-slots (dpa, otsa are considered) 1110 = not used pef 20450 / 20470 / 24470 register description preliminary data sheet 51 2001-11-20 preliminary 1111 = bit shift command (gi1 is considered to set shift value) (default: bit shift is inactive) i1..0 direction control 00 = set shift value for input line (spa is considered) 01 = set shift value for all input lines 10 = set shift value for all output lines 11 = set shift value for all lines (input and output) pef 20450 / 20470 / 24470 register description preliminary data sheet 52 2001-11-20 preliminary configuration command register 2 rd/wr address: 0a h reset value: 00h 76543210 cmd2 i3 i2 i1 i0 cc3 cc2 cc1 cc0 cc3..0 command code 0000 = no operation at all 0001 = external frequency (must be programmed first) i0 set external frequency 0 = 32.768 mhz 1 = 16.384 mhz i1 fallback to oscillator 0 = disable (and turn off ? enable ? status temporarily if fallback has occurred) 1 = enable if "fallback to oscillator" is enabled and a fallback has occurred, the corresponding failure is indicated in the iesta1 and/or iesta2 registers. for all clock failures, the pll bit ("pll source failure indication", iesta2 register) as well as the clock source related bit (in iesta1 or iesta2 register) will be set to "1". with the clock valid again the previously changed bits in iesta1 and/or iesta2 are set back to "0", the fallback must be disabled (cmd2=01 h /11 h ) for a few cycles and enabled again thereafter. i2 apll s parameters 0 = default 1 = start apll with improved parameters the command cmd2=41 h or cmd2=51 h to start the apll with improved parameters must only be issued only once after power up pef 20450 / 20470 / 24470 register description preliminary data sheet 53 2001-11-20 preliminary 0010 = parallel mode set the first 8 local bus input lines as 8 parallel input lines and set the first 8 local bus output lines as 8 parallel output lines. i0 set parallel mode 0 = disable 1 = enable 0011 = ireq pin command i1..0 set ireq pin (default: ireq is inactive) 00 = ireq is active low 01 = ireq is active high 10 = ireq as open-drain pin i2 set interrupt time-out counter set the inactive time between two consecutive interrupts 0 = disable = 20 ns 1 = enable = 300 ns 0100 = pcm standby command i0 set local bus (pcm) to high impedance 0 = outputs are tristated (default) 1 = outputs are enabled i1 not used must be set to ? 0 ? i2 not used must be set to ? 0 ? i3 internal pcm clock synchronization 0 = must be set in pcm clock master mode 1 = must be set in pcm clock slave mode 0101 = loop command i0 set pcm-pcm loop 0 = disable (default) 1 = enable 0110 = gpclk as frame signal command (gi1, gi2 are considered) (default: all gpclk ? s are tristated) i2..0 gpclk line (7..0) pef 20450 / 20470 / 24470 register description preliminary data sheet 54 2001-11-20 preliminary i3 invert mode 0 = frame signal is high active 1 = frame signal is low active 0111 = gpclk as clock signal command (gi1 is considered to set the frequency) (default: all gpclk ? s are tristated) i2..0 gpclk line (7..0) 1000 = set range of data rate command to avoid loss of data this command should be issued only once after reset. if the range of data rate is changed later on, loss of data must be expected for up to four frames. i3..0 range select to specify the range the min and max codes have to be logical or combined. 0001 = 2.048 mbit/s (default) 0010 = 4.096 mbit/s 0100 = 8.192 mbit/s 1000 = 16.384 mbit/s 1001 = read configuration i3..0 select configuration command 0000 = not used 0001 = pll source 0010 = not used 0011 = not used 0100 = not use 0101 = local bus (pcm) clock output selection 0110 = not used 0111 = not used 1000 = not used 1001 = phase alignment 1010 = external input frequency 1011 = parallel mode 1100 = ireq pin 1101 = local bus standby pef 20450 / 20470 / 24470 register description preliminary data sheet 55 2001-11-20 preliminary 1110 = loop 1111 = range of data rate 1010 = read gpclk configuration i2..0 gpclk line 7..0 1011 = read local bus (pcm) line configuration i0 destination information 0 = read data rate of input line (spa is considered) 1 = read data rate of output line (dpa is considered) 1100 = not used 1101 = read bit shift configuration i0 destination information 0 = shift value for input line (spa is considered) 1 = shift value for all output lines 1110 = not used 1111 = software reset i0 set software reset 0 = deactivate software reset (default) 1 = activate software reset pef 20450 / 20470 / 24470 register description preliminary data sheet 56 2001-11-20 preliminary message value register rd/wr address: 0c h reset value: 00h 76543210 mv mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 mv7..0 message value pef 20450 / 20470 / 24470 register description preliminary data sheet 57 2001-11-20 preliminary interrupt status register 1 rd address: 0e h reset value: 00h 76543210 ista1 apll 0 er2 er1 gpio tsa nfc rdy apll apll lock indication 0 = pll is not locked = bypassed 1 = pll is locked er2 error2 interrupt change indication (not active in 16-bit mode) 0 = no change detected in the interrupt error status register 2 (iesta2) 1 = change detected in the interrupt error status register 2 (iesta2) er1 error1 interrupt change indication 0 = no change detected in the interrupt error status register 1 (iesta1) 1 = change detected in the interrupt error status register 1 (iesta1) gpio general purpose change indication 0 = no change according to gp port inputs detected 1 = at least one change according to gp port inputs detected tsa time-slot arrived indication 0 = there is no new time-slot value in the register tsv 1 = there is a new time-slot value in the register tsv nfc no further connections indication 0 = establishing of connections is possible 1 = the maximum amount of connections is reached rdy ready indication 0 = ccmd is not ready to be written to 1 = ccmd is ready to be written to pef 20450 / 20470 / 24470 register description preliminary data sheet 58 2001-11-20 preliminary interrupt error status register 1 rd address: 10 h reset value: 00h for all these status bits the values can be interrupt error status register 2 rd address: 11 h reset value: 00h for all these status bits the values can be 76543210 iesta1000000nw2nw1 nw2 ntwk_2 failure indication nw1 ntwk_1 failure indication 0 = no failure detected 1 = failure detected 76543210 iesta2conpll000000 con connection memory error/overflow indication pll pll source failure indication 0 = no failure detected 1 = failure detected pef 20450 / 20470 / 24470 register description preliminary data sheet 59 2001-11-20 preliminary interrupt mask register 1 rd/wr address: 12 h reset value: 3dh mask = disable the interrupt 76543210 intm1 0 0 er2 er1 gpio tsa 0 rdy er2 error2 interrupt change indication mask (not active in 16-bit mode) 0 = do not mask the change indication bit 1 = mask the change indication bit er1 error1 interrupt change indication mask 0 = do not mask the change indication bit 1 = mask the change indication bit gpio general purpose change indication mask 0 = do not mask the change indication bit 1 = mask the change indication bit tsa time-slot arrived indication mask 0 = do not mask the time-slot arrived indication bit 1 = mask the time-slot arrived indication bit rdy ready indication mask 0 = do not mask the ready indication bit 1 = mask the ready indication bit pef 20450 / 20470 / 24470 register description preliminary data sheet 60 2001-11-20 preliminary interrupt error mask register 1 rd/wr address: 14 h reset value: 3fh for all these indication bits the values can be mask = disable the interrupt interrupt error mask register 2 rd/wr address: 15 h reset value: ffh for all these indication bits the values can be mask = disable the interrupt 76543210 intem1000000nw2nw1 nw2 ntwk_2 failure indication mask nw1 ntwk_1 failure indication mask 0 = do not mask this interrupt 1 = mask this interrupt 76543210 intem2conpll000000 con connection memory overflow indication mask pll pll source failure indication mask 0 = do not mask this interrupt 1 = mask this interrupt pef 20450 / 20470 / 24470 register description preliminary data sheet 61 2001-11-20 preliminary general purpose port input register rd address: 16 h reset value: 00h general purpose port output register wr address: 18 h reset value: 00h general purpose direction register rd/wr address: 1a h reset value: 00h 76543210 gppi gpb7 gpb6 gpb5 gpb4 gpb3 gpb2 gpb1 gpb0 gpb7..0 general purpose bits 76543210 gppo gpb7 gpb6 gpb5 gpb4 gpb3 gpb2 gpb1 gpb0 gpb7..0 general purpose bits 76543210 gpd dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 dc7..0 direction control 0 = set line as input 1 = set line as output pef 20450 / 20470 / 24470 register description preliminary data sheet 62 2001-11-20 preliminary general purpose mask register rd/wr address: 1b h reset value: ffh general purpose interrupt register rd address: 1c h reset value: idcode (hardware reset) 00 h (software reset) 76543210 gpm im7 im6 im5 im4 im3 im2 im1 im0 im7..0 gpio interrupt mask (bit 0 for line 0, bit 1 for line 1 ..) 0 = enable change detection 1 = disable change detection 76543210 gpi ind7 ind6 ind5 ind4 ind3 ind2 ind1 ind0 ind7..0 gpio interrupt indication (bit 0 for line 0, bit 1 for line 1 ..) 0 = no change detected 1 = at least one change detected on this line pef 20450 / 20470 / 24470 register description preliminary data sheet 63 2001-11-20 preliminary time-slot value register rd address: 1e h reset value: xxh for the read time-slot value command the content of the tsv register is interpreted as: for the read configuration command the content of the tsv register is interpreted as: 76543210 tsv tsv7 tsv6 tsv5 tsv4 tsv3 tsv2 tsv1 tsv0 tsv7..0 time-slot value pll reference configuration tsv3..0 see i3..0 from pll reference selection command (page 49 ) tsv6..4 000 = 8 khz 001 = 512 khz 010 = 1.536 mhz 011 = 1.544 mhz 100 = 2.048 mhz 101 = 4.096 mhz 110 = 8.192 mhz 111 = 16.384 mhz pcm clock output selection tsv3..0 see i3..0 from pcm clock output selection command (page 49 ) 00 = 8 khz 01 = 512 khz 10 = 2.048 mhz phase alignment tsv3 see i3 phase alignment command (page 50 ) external frequency tsv0 see i0 from set external frequency command (page 52 ) pef 20450 / 20470 / 24470 register description preliminary data sheet 64 2001-11-20 preliminary for the read gpclk configuration command the content of the tsv register is interpreted as: parallel mode tsv0 see i0 from set parallel mode command (page 53 ) ireq pin tsv2..0 see i1..0 from set ireq pin command (page 53 ) local bus (pcm) standby tsv1..0 see i0 from set local bus (pcm) standby command (page 53 ) loop tsv1..0 see i1..0 from loop command (page 53 ) range of data rate tsv3..0 see i3..0 from set range of data rate command (page 54 ) tsv0 0 = gpclk line as clock signal 1 = gpclk line as frame signal gpclk line as clock signal tsv3..1 000 = 8 khz 001 = 2.048 mhz 010 = 4.096 mhz 011 = 8.192 mhz 100 = 16.384 mhz 101 = input analog pll 110 = internal frequency gpclk line as frame signal tsv1 0 = rising edge 1 = falling edge tsv7..2 offset within the pfs frame in number of 16.384 mhz clock cycles (lower 6 bits; refer to con for the upper part) pef 20450 / 20470 / 24470 register description preliminary data sheet 65 2001-11-20 preliminary for the read local bus (pcm) line configuration command the content of the tsv register is interpreted as: in case of the read bit shift configuration command the content of the tsv register is interpreted as: tsv1..0 00 = 2.048 mbit/s 01 = 4.096 mbit/s 10 = 8.192 mbit/s 11 = 16.384 mbit/s tsv0 edge control 0 = rising edge 1 = falling edge tsv3..1 bit shift value (range: 7 to 0) tsv4 byte shift value (only for input lines) 0 = bit shift applies to byte before pfs rising edge 1 = bit shift applies to byte before pfs falling edge pef 20450 / 20470 / 24470 register description preliminary data sheet 66 2001-11-20 preliminary configuration register rd address: 1f h reset value: xxh for the memory dump command (ccmd) the content of the con register is: for the read gpclk configuration command the content of the con register is: 76543210 con con7 con6 con5 con4 con3 con2 con1 con0 con7..0 connection and data memory con7..5 width of the pulse in number of 16.384 mhz clock cycles from 1 to 8 i.e. con7..5 = 000 => 1 clock cycle, con7..5 = 010 => 3 clock cycles con4..0 offset within the pfs frame in number of 16.384 mhz clock cycles (upper 5 bits; refer to tsv for the lower part) pef 20450 / 20470 / 24470 register description preliminary data sheet 67 2001-11-20 preliminary 5.3 register overview for 16-bit interface table 16 register overview for 16-bit interface reg name access address reset value comment page no. sa rd/wr 00 h 0000 h source address register 68 da rd/wr 02 h 0000 h destination address register 68 gi rd/wr 04 h 0000 h general input register 69 cc16 rd/wr 06 h 0000 h connection command register 16-bit 69 cmd1 rd/wr 08h 00h configuration command register 1 this is a 8-bit register 49 cmd2 rd/wr 0ah 00h configuration command register 2 this is a 8-bit register 52 mv rd/wr 0ch 00h message value register this is a 8-bit register 56 ista1 rd 0eh 00h interrupt status register 1 this is a 8-bit register 57 iesta rd 10 h 0000 h interrupt error status register 70 intm1 rd/wr 12h 3dh interrupt mask register this is a 8-bit register 59 intem rd/wr 14 h ff3f h interrupt error mask register 70 idc rd 1c h idcode idcode register this is a 8-bit register 71 tsvc rd 1e h xxxx h time-slot value / configuration register 71 pef 20450 / 20470 / 24470 register description preliminary data sheet 68 2001-11-20 preliminary 5.4 detailed register description for 16-bit interface source address register rd/wr address: 00 h reset value: 0000 h destination address register rd/wr address: 02 h reset value: 0000 h 15 14 13 12 11 10 9 8 tsa7 tsa6 tsa5 tsa4 tsa3 tsa2 tsa1 tsa0 sa 76543210 0 0 0 0 pa3 pa2 pa1 pa0 high see input time-slot address register on page 42 low see source port address register on page 42 15 14 13 12 11 10 9 8 tsa7 tsa6 tsa5 tsa4 tsa3 tsa2 tsa1 tsa0 da 76543210 0 0 0 0 pa3 pa2 pa1 pa0 high see output time-slot address register on page 43 low see destination port address register on page 42 pef 20450 / 20470 / 24470 register description preliminary data sheet 69 2001-11-20 preliminary general input register rd/wr address: 04 h reset value: 0000 h connection command register 16-bit rd/wr address: 06 h reset value: 0000 h 15 14 13 12 11 10 9 8 gv15 gv14 gv13 gv12 gv11 gv10 gv9 gv8 gi 76543210 gv7gv6gv5gv4gv3gv2gv1gv0 gv15..0 general value gv15..8 see general input register 2 on page 46 gv7..0 see general input register 1 on page 44 15 14 13 12 11 10 9 8 0 0 osca2 osca1 osca0 isca2 isca1 isca0 cc16 76543210 i3 i2 i1 i0 cc3 cc2 cc1 cc0 high see subchannel address register on page 43 low see connection command register on page 47 pef 20450 / 20470 / 24470 register description preliminary data sheet 70 2001-11-20 preliminary interrupt error status register rd address: 10 h reset value: 0000 h interrupt error mask register rd/wr address: 14 h reset value: ff3f h 15 14 13 12 11 10 9 8 conpll000000 iesta 76543210 000000nw2nw1 high see interrupt error status register 2 on page 58 low see interrupt error status register 1 on page 58 15 14 13 12 11 10 9 8 conpll000000 intem 76543210 000000nw2nw1 high see interrupt error mask register 2 on page 60 low see interrupt error mask register 1 on page 60 pef 20450 / 20470 / 24470 register description preliminary data sheet 71 2001-11-20 preliminary idcode register rd address: 1c h reset value: idcode time-slot value / configuration register rd address: 1e h reset value: xxxx h 76543210 idc idc7 idc6 idc5 idc4 idc3 idc2 idc1 idc0 idc7..0 idcode refer to table 11 "idcode via p read access" on page 38 15 14 13 12 11 10 9 8 tsvc15 tsvc14 tsvc13 tsvc12 tsvc11 tsvc10 tsvc9 tsvc8 tsvc 76543210 tsvc7 tsvc6 tsvc5 tsvc4 tsvc3 tsvc2 tsvc1 tsvc0 tsvc15..8 configuration and connection data memory (refer to page 66 ) tsvc7..0 time-slot value (refer to page 63 ) pef 20450 / 20470 / 24470 programming the device preliminary data sheet 72 2001-11-20 preliminary 6 programming the device the register set consists of parameter registers ( spa , itsa , sca , dpa , otsa , gi1 ..), command registers ( ccmd , cmd1 , cmd2 ) and status registers ( ista1 , iesta1 , iesta2 ). please note that some bits contained in the register ista1 (interrupt status register 1) do not generate any interrupt, for more details see the paragraph chapter 6.2 . before issuing a command the parameter registers have to be written accordingly. a connection command can only be issued if the connection command register is ready to be written to (see figure 15 ). the connection command register status is shown with the rdy bit in the ista1 register. a detailed description for the read and write access to the command registers can be found in chapter 6.1 . figure 15 order of register access command register ready? write parameter registers write command register n y command register ready? write parameter registers write command register n y passive waiting with interrupt active waiting (polling) without interrupt switi_032.emf pef 20450 / 20470 / 24470 programming the device preliminary data sheet 73 2001-11-20 preliminary 6.1 read and write access for the read and write access it is necessary to distinguish between a connection and configuration command. the connection command register is used to establish a connection (described in chapter 6.10 ) and the configuration registers are used to configure the device, e.g. set the clock frequency. if the ista1 :rdy bit is set the connection command register is ready to receive data from the p interface. if the parameter register and the connection command register are written the rdy bit will be reset from the internal controller. if the connection is established the internal controller will set the rdy bit and the connection command register is ready for the next write or read access. the ista1 :rdy can be enabled to generate an interrupt to indicate that the device is ready to receive the data, otherwise the p must poll the ista1 :rdy bit. the configuration command register works independent from the rdy bit. note: there must be a recovery time period of 120 ns after every configuration command write access to the next write access (command or parameter register). pef 20450 / 20470 / 24470 programming the device preliminary data sheet 74 2001-11-20 preliminary 6.2 interrupt handling the switi interrupt concept consists of four interrupt status register with their corresponding mask register. the five interrupt status register can be divided in one main register, and a sub group including two error interrupt register, one general purpose interrupt register and one time-slot value register. every sub register has a bit in the main register to indicate the set of an interrupt in the assigned error or general purpose register or to indicate a new value in the time-slot value register. the interrupt status register can be read via the microprocessor interface. the nfc and rdy will be set and reset from the internal controller. when an interrupt occurs one or more of the bit gpio, tsa, er2, or er1 is set, then the assigned secondary interrupt status register or time-slot value register must be read first in order to check for the cause of the interrupt. after a secondary status register read access, the error status register and the corresponding bit in the interrupt status register 1 ( ista1 ) will be reset. figure 16 8-bit p access interrupt structure the ireq output is level active. it stays active until all interrupt sources have been serviced. if a new status bit is set while an interrupt is being serviced (p read access), the ireq pin stays active. for the duration of a write access to the intm1 register the ireq line is deactivated. when using an edge-triggered interrupt controller, it is recommended to rewrite the intm1 register at the end of any interrupt service routine. apll, str, rdy and nfc bits if the internal controller does set the rdy bit for the first time and the bit is not masked an interrupt will be generated. if the p reads the ista1 register the interrupt will be deactivated. the rdy bit is still active and can be reset from the internal controller. the nfc, str and apll bits are not set by any interrupt and therefore can not be masked. setting these bit does not generate any interrupt. the nfc bit is set from the internal controller if no further connections can be established. the str bit is set from the internal stream to stream controller if a stream to stream connection is configured. the apll bit is set from the internal analog pll controller if the pll is locked. interrupt error status register 2 interrupt error status register 1 time slot value register general purpose interrupt status register switi_063.emf apll er2 er1 gpio tsa nfc rdy main status register pef 20450 / 20470 / 24470 programming the device preliminary data sheet 75 2001-11-20 preliminary masking interrupts if an interrupt is not masked (enabled) the ireq pin will be active if one of the status bits in the interrupt status register is set. the mask bit prevents that the ireq pin will be active if the status bit is set. the mask bits for the error status registers or general purpose interrupt register disable the interrupt indication for the interrupt status register. only the interrupt status register can set the ireq pin if the bit is not masked. interrupt structure for a 16-bit microprocessor access figure 17 16-bit p access interrupt structure in opposite to the 8-bit p access there is only one bit (er1) to indicate a change in the 16-bit interrupt error status register 1. er1 gpio tsa nfc rdy interrupt error status register 1 time slot value register switi_068.emf apll pef 20450 / 20470 / 24470 programming the device preliminary data sheet 76 2001-11-20 preliminary 6.3 command and register overview the following table ( table 17 ) shows which parameter registers are considered by issuing an appropriate connection command. table 17 affected registers for connection commands command registers spa itsa sca dpa otsa mv gi1 gi2 con connect/disconnect (without subchannels) xx x x connect (with subchannels) xx xx x disconnect (with subchannels) xx x x send message x x x stop message x x disconnect part of broadcast (without subchannels) xx x x disconnect part of broadcast (with subchannels) xx xx x multipoint connect/ disconnect xx x x bidirectional connection x x x x disconnect all memory dump (connection and data memory) x pef 20450 / 20470 / 24470 programming the device preliminary data sheet 77 2001-11-20 preliminary the following table ( table 18 ) shows which parameter registers are considered by issuing an appropriate configuration command. table 18 affected registers for configuration commands command registers cmd1 cmd2 spa itsa sca dpa otsa gi1 gi2 tsv pll reference x x pcm clock output x phase alignment x set bit rate local bus xx x read time-slot x x x x x clock shift x x x external input frequency x set parallel mode x set ireq pin x standby local bus x set loop x frame signal x x x gpclk clock x x set range of data rate x read configuration xx read gpclk configuration xx read local bus configuration xx read bit shift configuration xx software reset x pef 20450 / 20470 / 24470 programming the device preliminary data sheet 78 2001-11-20 preliminary the command registers have the following structure: cc3..0 is the command code and i3..0 is the parameter code. the following tables ( table 19 to table 20 ) show all valid values of command and parameter codes and the related function. 76543210 i3 i2 i1 i0 cc3 cc2 cc1 cc0 table 19 connection command and parameter codes command 1) 1) the input port is determined in spa bit3..0 and the output port in dpa bit3..0. the input time-slot is determined in itsa and the output time-slot in otsa. command code (low nibble) parameter code (high nibble) note constant delay connect disconnect 1 h 5 h 0 h 1 h 2 h 3 h address 8-bit connections address 4-bit connections address 2-bit connections address 1-bit connections minimum delay connect 2 h x h send message 3 h x h stop message 4 h x h disconnect part of broadcast 6 h 0 h 1 h 2 h 3 h address 8-bit connections address 4-bit connections address 2-bit connections address 1-bit connections multipoint connect 7 h 0 h 1 h or connection of time-slots and connection of time-slots disconnect all 8 h x h bidirectional connect 9 h 0 h 1 h minimum delay constant delay memory dump a h 0 h 1 h disable enable pef 20450 / 20470 / 24470 programming the device preliminary data sheet 79 2001-11-20 preliminary table 20 configuration command 1 and parameter codes command command code (low nibble) parameter code (high nibble) note set bit rate local bus 1) 1) the input and output port is determined in spa , dpa b h 0-3 h 4-7 h 8-b h c-f h no effect set bit rate of local input port (2/4/8/ 16 mbit/s) set bit rate of local output port (2/4/8/16 mbit/s) set for both input and output (2/4/8/16 mbit/s) read time-slot 2) 2) the time-slot is determined in spa and itsa or dpa and otsa d h 0 h 1 h read time-slot of input port read time-slot of output port bit shift 3) 3) the input line is determined in spa , the shift information in gi1 f h 0 h 1 h 2 h 3 h set bit shift of input line set bit shift of all input lines set bit shift of all output lines set bit shift of all input and output lines table 21 configuration command 2 and parameter code command command code (low nibble) parameter code (high nibble) note external frequency 1 h 0 h 1 h set frequency to 32.768 mhz set frequency to 16.384 mhz parallel mode 2 h 0 h 1 h disable enable = first 8 local input bus lines are parallel and first 8 local output lines are parallel set ireq pin 3 h 0 h 1 h 2 h 4 h 5 h 6 h ireq is active low, timer = 20 ns ireq is active high, timer = 20 ns ireq as open-drain, timer = 20 ns ireq is active low, timer = 300 ns ireq is active high, timer = 300 ns ireq as open-drain, timer = 300 ns pef 20450 / 20470 / 24470 programming the device preliminary data sheet 80 2001-11-20 preliminary standby local bus 4 h 0 h 1 h disable local bus (pcm) enable local bus (pcm) loop 5 h 0 h 1 h no loop at all enable local bus loop frame signal 1) 6 h 0xxx b 1xxx b signal is high active signal is low active xxx is the line address gpclk as clock 2) 7 h 0 h -7 h parameter code is line address range of data rate 8 h 0 h -6 h 8 h -a h logical or connection from min. and max. codes read configuration 3) 9 h 0 h 1 h 5 h 9 h a h b h c h d h e h f h master/slave configuration pll reference clock output selection phase alignment external input frequency parallel mode ireq pin standby local bus loop range of data rate read gpclk configuration 4) a h 0 h -7 h parameter code is line address read local bus line configuration 5) b h 0 h 1 h data rate of input line 6) data rate of output line 7) read bit shift configuration 8) d h 0 h 1 h shift value for input line 9) shift value for all output lines 1) offset and width are determined in gi1 and gi2 2) frequency is determined in gi1 3) the result can be read from the tsv register 4) the result can be read from the tsv and con register 5) the result can be read from the tsv register 6) spa must be used for line number 7) dpa must be used for line number 8) the result can be read from the tsv register table 21 configuration command 2 and parameter code (cont ? d) command command code (low nibble) parameter code (high nibble) note pef 20450 / 20470 / 24470 programming the device preliminary data sheet 81 2001-11-20 preliminary 6.4 indirect configuration register access it is possible to read the current switi configuration with an indirect register access for analyze and test purpose. there are five commands in the cmd2 register which can be used to read the configuration. the clock generator output signal and external configuration for the switi can be read with the ? read configuration command ? . the four instruction bits select one possible configuration command. the current configuration is determined by the command written in the tsv register. the configuration information for every command can be found on page 40 . the line configuration can be read with the command ? read local bus line configuration ? . before the command will be issued the spa or dpa register must be written with the port number. the configuration for the selected line is written in the tsv register by the internal controller. the interrupt handling is described in chapter 6.2 . the bit shift configuration can be read with the command ? read bit shift configuration ? and the dataflow is the same as described above. with the command ? read gpclk configuration ? it is possible to read the configuration for every gpclk line. if this command is written the configuration can be read from the tsv and con register. the con register is not interrupt controlled and will keep the last data after a microprocessor read access. to read the correct configuration data from the tsv register it is not allowed to use the command "read time-slot value" before the tsv register was read. pef 20450 / 20470 / 24470 programming the device preliminary data sheet 82 2001-11-20 preliminary 6.5 initialization procedure after the reset process the pll, local bus (pcm) interface, and some other signals need to be initialized. since the switi offers the possibility to use two different external crystal/oscillator frequencies the command ? set external frequency ? must be used first to set the correct frequency and to set the correct value of the input frequency for the apll. after approximately 750s the apll is locked and the apll status bit is set and the next commands can be written. figure 18 initialization procedure after reset after this initialization procedure the different functional blocks of the switi can be programmed. ? local bus (pcm) interface ? interrupt ? s and ireq pin ? gpclk ? s and frame signals ? general purpose interface reset (hardware) internal frequency = ext. frequency write 41 h to c m d 2 (if ext. freq. = 32.768 m h z) write 51 h to c m d 2 (if ext. freq. = 16.384 m h z) wait ~750s read interrupt status register 1 ista1:apll = 1 ? apll is locked int. frequency = 49.152 mhz y n switi_073.emf pef 20450 / 20470 / 24470 programming the device preliminary data sheet 83 2001-11-20 preliminary 6.6 clocking unit the pcm clock signals for the line interface will be provided from external pcm devices if the switi is used as pcm clock slave or will be provided from the internal pll if the switi is used as pcm clock master. this pcm clock configuration can be programmed with the special command ? pcm input/output selection ? in the figure cmd1 register. for the pll synchronization please refer to chapter 3.4.4 on page 27 . example: switi as pcm clock master, pll reference is ntwk_1 with 8 khz and pdc is driven with 8.192 mhz and pfs is driven. ? write 00 h to gi1 ? write 52 h to cmd1 ? write b6 h to cmd1 example switi as pcm clock slave, pll reference is pdc with 4.096 mhz. ? write 05 h to gi1 ? write 22 h to cmd1 ? write 26 h to cmd1 (pdc = 4.096 mhz and pfs as input) pef 20450 / 20470 / 24470 programming the device preliminary data sheet 84 2001-11-20 preliminary 6.7 local bus (pcm) line interface 6.7.1 standby command all pcm data lines are in a high impedance state after the reset process. if they are configured (data rate, bit shift) they can be enabled with the standby command. during the normal operation the pcm lines can be enabled or disabled with the standby command. if the lines are disabled the device works internally like an active device. example: set all output pcm lines to high impedance. ? write 04 h to cmd1 6.7.2 determining clock rates the data rate range command is necessary to optimize the minimum delay feature. after the reset process the device assumes a bit rate of 2.048 mbit/s for all pcm lines. the command must be issued if other data rates are used. example (8-bit p interface): 1. specify that only 2.048 mbit/s and 4.096 mbit/s are used for following set bit rate command. ? write 38 h to cmd2 2. set bit rate of 4.096 mbit/s on local bus input line 8 and local bus output line 1 ? write 08 h to spa ? write 01 h to dpa ? write db h to cmd1 example (16-bit p interface): 1. ? write 38 h to cmd2 2. ? write 0008 h to sa ? write 0001 h to da ? write db h to cmd1 pef 20450 / 20470 / 24470 programming the device preliminary data sheet 85 2001-11-20 preliminary 6.7.3 performing bit shifting the bit shift is performed on half-bit steps, not on a clock basis. it is a true bit shift, it means that with a data rate equals to the data clock frequency (e.g. 4.096 mbit/s with 4.096 mhz data clock) programming a bit shift of 1-bit results on a shift of 1 clock period, and programming a shift of half-bit the result is a shift of half clock period. running in double data clock rate (e.g. 4.096 mbit/s with 8.192 mhz data clock), a bit shift of 1-bit results on a shift of 2 clock periods and a shift of half-bit will result on a shift of 1 clock period. 6.7.3.1 input bit shifting figure 19 example: input bit shifting example (8-bit p interface): begin time-slot 0 of local input line 8 with the 4th rising edge relative to one byte before the pfs rising edge. the bits are internally sampled with the falling edge. ? write 08 h to spa ? write 08 h to gi1 ? write 0f h to cmd1 example (16-bit p interface): ? write 0008 h to sa ? write 0008 h to gi ? write 0f h to cmd1 pfs 0 1 7 local-bus input line 8 23 ts 0 4 switi_040.em f 0 data rate of selected line pef 20450 / 20470 / 24470 programming the device preliminary data sheet 86 2001-11-20 preliminary 6.7.3.2 output bit shifting figure 20 example: output bit shifting example (8-bit p interface): output time-slot 0 of all output lines begins with the first falling edge relative to the first byte after pfs rising edge. the bits are internally sampled with the rising edge. ? write 01 h to gi1 ? write 2f h to cmd1 example (16-bit p interface): ? write 0001 h to gi ? write 2f h to cmd1 pfs 0 1 7 local-bus output lines 2 ts 0 switi_041.emf data rate of line pef 20450 / 20470 / 24470 programming the device preliminary data sheet 87 2001-11-20 preliminary 6.8 global clock signals 6.8.1 framing groups figure 21 example framing groups example (8-bit p interface): frame signal on gpclk_1 starts with the rising edge of 64th clock cycle and the length is set to 244 ns (4 x 61 ns). ? write 00 h to gi1 ? write 61 h to gi2 ? write 16 h to cmd2 frame signal on gpclk_2 starts with the falling edge of the 4th clock cycle and the length is set to 427 ns (7 x 61 ns). ? write 12 h to gi1 ? write c0 h to gi2 ? write 26 h to cmd2 example (16-bit p interface): ? write 6100 h to gi2 ? write 0016 h to cmd2 ? write c012 h to gi2 ? write 0026 h to cmd2 125s 01 125s 64 01 4 4 pfs 16.384 mbit/s gpclk_1 gpclk_2 switi_077.emf 427ns 244ns 125s pef 20450 / 20470 / 24470 programming the device preliminary data sheet 88 2001-11-20 preliminary 6.9 read time-slot value by issuing this command the time-slot value appears in the register tsv after arriving and an interrupt will be caused and a new read time-slot value will be accepted. the command has to be issued for every read request. the current tsv data will be overwritten if the read time-slot command is issued. example (8-bit p interface): read time-slot 10 of local bus input line 3 ? write 03 h to spa ? write 0a h to itsa ? write 0d h to cmd1 example (16-bit p interface): ? write 0a03 h to sa ? write 0d h to cmd1 wrong time-slot and time-out in some case it could be happen that the p tries to read a wrong time-slot. a wrong time- slot is defined as an invalid time-slot number for the selected data rate, e.g. data rate = 2 mbit/s and selected time-slot is 58. if the p tries to read a wrong time-slot no interrupt would be generated and the controller doesn ? t accept any further commands. the switi has an integrated time-out counter to allow a new read time-slot command after the maximum of three frames. pef 20450 / 20470 / 24470 programming the device preliminary data sheet 89 2001-11-20 preliminary 6.10 establish connections the following chapter describes the programming of several kinds of connections. the programming interface allows to program or re-program a connection during the normal switching mode. before a new connection for a specific output time-slot and line will be programmed the specific connection has to be released. 6.10.1 establish 8-bit connections figure 22 example: 8-bit connection example (8-bit p interface): connect time-slot 10 of local bus input line 3 with output time-slot 30 of local bus output line 13 as a constant delay connection ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 0d h to dpa ? write 01 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e0d h to da ? write 0001 h to cc16 local-bus input line 3 local-bus output line 13 constant delay frame signal ts 30 ts 10 switi_027.emf pef 20450 / 20470 / 24470 programming the device preliminary data sheet 90 2001-11-20 preliminary 6.10.2 subchannel switching with the subchannel address register ( sca ) and the constant delay command it is possible to program 1,2, and 4 connections. the following figure explains the relation between the subchannel address and the corresponding bits in one time-slot. figure 23 subchannel address in time-slot 6.10.2.1 establish 4-bit connections figure 24 example: 4-bit connection 1 0 isca from sca register osca from sca register 1 2 3 0 3 1 2 4 0 5 6 7 1 3 2 0 1 0 2 3 ts in 6 1 3 4 0 5 2 7 1 0 2 3 1 0 ts out 0 h 1 h 1 h 6 h 1 h 3 h 2 h 3 h switi_070.emf local-bus input line 3 local-bus output line 13 constant delay frame signal ts 30 ts 10 switi_028.emf pef 20450 / 20470 / 24470 programming the device preliminary data sheet 91 2001-11-20 preliminary example (8-bit p interface): connect low nibble of time-slot 10 of local bus input line 3 with high nibble of output time- slot 30 of local bus output line 13 as a constant delay connection ? write 08 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 0d h to dpa ? write 11 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e0d h to da ? write 0811 h to cc16 6.10.2.2 establish 2-bit connections figure 25 example: 2-bit connection example (8-bit p interface): connect 2nd 2-bit subchannel of time-slot 10 of local bus input line 3 with 4th 2-bit subchannel of output time-slot 30 of local bus output line 13 as a constant delay connection ? write 19 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 0d h to dpa ? write 21 h to ccmd local-bus input line 3 local-bus output line 13 constant delay frame signal ts 30 ts 10 switi_042.emf pef 20450 / 20470 / 24470 programming the device preliminary data sheet 92 2001-11-20 preliminary example (16-bit p interface): ? write 0a03 h to sa ? write 1e0d h to da ? write 1921 h to cc16 6.10.2.3 establish 1-bit connections figure 26 example: 1-bit connection example (8-bit p interface): connect 3rd 1-bit subchannel of time-slot 10 of local bus input line 3 with 6th 1-bit subchannel of output time-slot 30 of local bus output line 13 as a constant delay connection ? write 2a h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 0d h to dpa ? write 31 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e0d h to da ? write 2a31 h to cc16 local-bus input line 3 loca-bus output line 13 constant delay frame signal ts 30 ts 10 switi_043.emf pef 20450 / 20470 / 24470 programming the device preliminary data sheet 93 2001-11-20 preliminary 6.10.3 establish broadcast connections figure 27 example: broadcast connection example (8-bit p interface): connect time-slot 10 of local bus line 3 with output time-slot 30 of local bus output line 13 and output time-slot 98 of local bus output line 15 in constant delay mode. if the connections are established consecutively it is not necessary to rewrite the source determining registers itsa and spa because they keep their values. ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 0d h to dpa ? write 01 h to ccmd ? write 62 h to otsa ? write 0f h to dpa ? write 01 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e0d h to da ? write 0001 h to cc16 ? write 620f h to da ? write 0001 h to cc16 local-bus input line 3 local-bus output line 13 constant delay frame signal ts 30 ts 10 local-bus output line 15 ts 98 switi_031.emf pef 20450 / 20470 / 24470 programming the device preliminary data sheet 94 2001-11-20 preliminary 6.10.4 establish subchannel broadcast connection figure 28 example: subchannel broadcast connection ? first connection ? write 03 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 21 h to ccmd ? second connection ? write 1a h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 21 h to ccmd ? third connection ? write 23 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 31 h to ccmd ? fourth connection ? write 2a h to sca ? write 0a h to itsa ? write 03 h to spa local-bus input line 3 local-bus output line 0 constant delay frame signal ts 30 ts 10 switi_081.emf 1 2 3 4 5 pef 20450 / 20470 / 24470 programming the device preliminary data sheet 95 2001-11-20 preliminary ? write 1e h to otsa ? write 00 h to dpa ? write 31 h to ccmd ? fifth connection ? write 08 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 21 h to ccmd 6.10.5 establish multipoint connection figure 29 example: multipoint connection example (8-bit p interface): connect time-slot 10 of local bus line 3 and time-slot 20 of local bus line 8 logical or with output time-slot 30 of local bus output line 13 in constant delay mode. if the connections are established consecutively it is not necessary to rewrite the destination determining registers otsa and dpa because they keep their values. ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 0d h to dpa ? write 07 h to ccmd ? write 14 h to itsa ? write 08 h to spa ? write 07 h to ccmd local-bus input line 3 local-bus output line 13 constant delay frame signal ts 30 ts 10 local-bus input line 8 ts 20 or switi_034.emf pef 20450 / 20470 / 24470 programming the device preliminary data sheet 96 2001-11-20 preliminary example (16-bit p interface): ? write 0a03 h to sa ? write 1e0d h to da ? write 0007 h to cc16 ? write 1408 h to sa ? write 0007 h to cc16 6.11 send messages sending messages means to transmit a constant value on any time-slot or subchannel after the message is programmed within three frames. a message is sent continuously until the sending is stopped by the stop message command. figure 30 example: send message example (8-bit p interface): send constant value of ff h on time-slot 10 of local bus line 3 ? write ff h to mv ? write 0a h to otsa ? write 03 h to dpa ? write 03 h to ccmd example (16-bit p interface): ? write ff h to mv ? write 0a03 h to da ? write 0003 h to cc16 local-bus output line 3 ts 10 ff h frame signal switi_029.emf pef 20450 / 20470 / 24470 programming the device preliminary data sheet 97 2001-11-20 preliminary 6.12 release connections 6.12.1 release 8-bit connections example (8-bit p interface): release connection established in figure 22 ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 0d h to dpa ? write 05 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e0d h to da ? write 0005 h to cc16 6.12.2 release 4-bit connections example (8-bit p interface): release connection established in figure 24 ? write 08 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 0d h to dpa ? write 15 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e0d h to da ? write 0815 h to cc16 6.12.3 release 2-bit connections example (8-bit p interface): release connection established in figure 25 ? write 19 h to sca ? write 0a h to itsa ? write 03 h to spa pef 20450 / 20470 / 24470 programming the device preliminary data sheet 98 2001-11-20 preliminary ? write 1e h to otsa ? write 0d h to dpa ? write 25 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e0d h to da ? write 1925 h to cc16 6.12.4 release 1-bit connections example (8-bit p interface): release connection established in figure 26 ? write 2a h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 0d h to dpa ? write 35 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 1e0d h to da ? write 2a35 h to cc16 pef 20450 / 20470 / 24470 programming the device preliminary data sheet 99 2001-11-20 preliminary 6.12.5 release broadcast connection example (8-bit p interface): release connection established in figure 27 . all but the last connection participating on a broadcast connection have to be released by the disconnect part of the broadcast command. the last connection has to be released by the constant delay connect disconnect command. ? write 0a h to itsa ? write 03 h to spa ? write 62 h to otsa ? write 0f h to dpa ? write 06 h to ccmd ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 0d h to dpa ? write 05 h to ccmd example (16-bit p interface): ? write 0a03 h to sa ? write 620f h to da ? write 0006 h to cc16 ? write 0a03 h to sa ? write 1e0d h to da ? write 0005 h to cc16 6.12.6 release subchannel broadcast connection the order can be different as the establish order. the last release must be a normal release command. ? first connection ? write 03 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 26 h to ccmd ? second connection ? write 1a h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa pef 20450 / 20470 / 24470 programming the device preliminary data sheet 100 2001-11-20 preliminary ? write 00 h to dpa ? write 26 h to ccmd ? third connection ? write 23 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 36 h to ccmd ? fourth connection ? write 2a h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 36 h to ccmd ? fifth connection ? write 08 h to sca ? write 0a h to itsa ? write 03 h to spa ? write 1e h to otsa ? write 00 h to dpa ? write 25 h to ccmd 6.12.7 release multipoint connection this type of connections is released with normal disconnect commands. (see ? release 8-bit connections ? on page 97.) 6.13 stop sending messages example (8-bit p interface): stop sending message invoked in figure 30 ? write 0a h to otsa ? write 03 h to dpa ? write 04 h to ccmd example (16-bit p interface): ? write 0a03 h to da ? write 0004 h to cc16 pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 101 2001-11-20 preliminary 7 timing diagrams 7.1 pcm interface timing the following tables and figures give the pcm timing with a capacitive load of 50 pf. pdc and pfs are configured as inputs. the timing is also valid if pdc and pfs are configured as outputs.the pfs output high time is fixed to 488 ns for all data rates and clock rates.the pfs input minimum high time depends on the pdc input frequency (see table 22 ). figure 31 pcm timing t d o u t t sin t h i n t clk_h t f s pfs pdc in out t clk_l t hfs t f t r bit 7 bit 6 bit 7 bit 6 t p f s switi_057.emf t sfs ts0 ts63 4mbit/s pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 102 2001-11-20 preliminary table 22 pcm timing parameter symbol limit values unit test condition min. max. period pfs t pfs 125 s pfs high time t fs 480 ns pdc = 2.048 mhz pfs set up time to clock t sfs 15 ns pfs hold time from clock t hfs 20 ns pfs high time t fs 240 ns pdc = 4.096 mhz pfs set up time to clock t sfs 15 ns pfs hold time from clock t hfs 20 ns pfs high time t fs 120 ns pdc = 8.192 mhz pfs set up time to clock t sfs 10 ns pfs hold time from clock t hfs 20 ns pfs high time t fs 60 ns pdc = 16.384 mhz pfs set up time to clock t sfs 10 ns pfs hold time from clock t hfs 20 ns pdc clock period t clk 480 ns pdc = 2.048 mhz pdc clock period low t clk_l 232 251 ns pdc clock period high t clk_h 233 252 ns pdc clock period t clk 240 ns pdc = 4.096 mhz pdc clock period low t clk_l 112 131 ns pdc clock period high t clk_h 113 132 ns pdc clock period t clk 120 ns pdc = 8.192 mhz pdc clock period low t clk_l 51 70 ns pdc clock period high t clk_h 52 71 ns pdc clock period t clk 60 ns pdc = 16.384 mhz pdc clock period low t clk_l 26 34 ns pdc clock period high t clk_h 27 35 ns pdc rise time t r 10 ns pdc fall time t f 10 ns pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 103 2001-11-20 preliminary serial data input set up time t sin 20 ns pdc = 2.048 mhz serial data input hold time t hin 30 ns serial data input set up time t sin 20 ns pdc = 4.096 mhz serial data input hold time t hin 30 ns serial data input set up time t sin 20 ns pdc = 8.192 mhz serial data input hold time t hin 30 ns serial data input set up time t sin 20 ns pdc = 16.384 mhz serial data input hold time t hin 30 ns serial data output delay t dout 030 1) ns pdc = 2.048 mhz serial data output delay t dout 030 1) ns pdc = 4.096 mhz serial data output delay t dout 030 1) ns pdc = 8.192 mhz serial data output delay t dout 030 1) ns pdc = 16.384 mhz 1) for pcm master, the maximum delay is 15 ns. table 22 pcm timing (cont ? d) parameter symbol limit values unit test condition min. max. pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 104 2001-11-20 preliminary 7.2 pcm parallel mode timing figure 32 parallel mode timing table 23 pcm parallel mode timing parameter symbol limit values unit test condition min. max. frame setup time to clock t fs 125 ns frame hold time to clock t fh 125 ns input data setup time t ds 50 ns input data hold time t dh 15 ns output data delay t dd 35 ns pdc clock period t clk 483 493 ns pdc = 2.048 mhz pdc clock period high t clk_h 231 257 ns pdc clock period low t clk_l 231 257 ns switi_071.emf time slot pdc pfs in out 2550123 t fs t fh t clk t clk_h t dh t ds t dd ts1 valid data ts3 valid data t clk_l pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 105 2001-11-20 preliminary 7.3 microprocessor interface timing microprocessor accesses of the switi are performed by an activation of the address and cs . ? by driving the mode16 pin ? low ? the user selects the 8-bit microprocessor interface, by driving it ? high ? - the 16-bit microprocessor interface. ? by driving the ale pin ? high ? the user selects intel/infineon mode, by driving it ? low ? - motorola mode. the pin is sampled during the hardware reset process. ? in intel/infineon mode, a distinction is needed between working in multiplexed address/data bus mode and de-multiplexed address and data bus mode. in motorola mode, only de-multiplexed busses are used. by driving the ale pin ? high ? during the normal operation the user selects the de-multiplexed mode, a falling or rising edge during the normal operation selects the multiplexed mode. 7.3.1 infineon/intel timing in de-multiplexed mode in this mode driving rd ? low ? causes a read access, driving wr ? low ? causes a write access. in de-multiplexed bus configuration, ale must be driven ? high ? . note: the read/write recovery time (t ri and t wi ) are required only for consecutive accesses to the microprocessor interface table 24 infineon/intel timing in de-multiplexed mode parameter symbol limit values (c load = 50pf) min max address setup time to wr or rd t as 15 ns rd pulse width t rr 60 ns rd recovery time t ri 120 ns data output delay from rd active t rd 60 ns data float delay from rd inactive t df 15 ns wr pulse width t ww 40 ns wr recovery time t wi 120 ns data setup time to wr x cs t dw 20 ns data hold time from wr x cs t wd 10 ns pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 106 2001-11-20 preliminary . figure 33 infineon/intel read cycle in de-multiplexed mode figure 34 infineon/intel write cycle in de-multiplexed mode addresses will be latched with the falling wr edge during the write cycle internally. 7.3.2 infineon/intel timing in multiplexed mode in this mode the ale pin is used to lock the address send via the multiplexed a/d bus. address data t rd t rr tt ri t t df t as a0-a4 rd xcs d0-d7 address data t ww t t wi t dw t t wd t as a0-a4 wr xcs d0-d7 pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 107 2001-11-20 preliminary figure 35 infineon/intel read cycle in multiplexed mode table 25 infineon/intel timing in multiplexed mode parameter symbol limit values (c load = 50pf) min max ale pulse width t aa 15 ns address setup time to ale falling edge t al 15 ns address hold time from ale falling edge t la 5ns address latch setup time to wr , rd t als 5ns rd pulse width t rr 60 ns rd recovery time t ri 120 ns data output delay from rd active t rd 60 ns data float delay from rd inactive t df 15 ns wr pulse width t ww 40 ns wr recovery time t wi 120 ns data setup time to wr x cs t dw 20 ns data hold time from wr x cs t wd 10 ns address data address t rd t rr t t la t al t ri t df t als t aa ale rd xcs ad0-ad7 pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 108 2001-11-20 preliminary figure 36 infineon/intel write cycle in multiplexed mode 7.3.3 motorola microprocessor timing in this mode r/w distinguishes between read and write interactions, and ds is used for timing. ds x cs is active (low) when both, ds and cs , are active (low). the ale pin must be driven ? low ? . note: ds x cs is active (low) when, both, ds and cs are active (low) table 26 motorola timing parameter symbol limit values (c load = 50pf) min max address setup time to csxds t as 15 ns r or w setup to ds t dsd 0 r/w hold from csxds inactive t rwd 0 r pulse width t rr 60 ns r recovery time t ri 120 ns data output delay from r t rd 60 ns data float delay from r t df 15 ns w pulse width t ww 40 ns w recovery time t wi 120 ns data setup time to w and cs , ds and cs t dw 10 ns data hold time from w and cs , ds and cs t wd 10 ns address data address t ww t t dw t la t al t wi t wd t t als t aa t ale wr xcs ad0-ad7 pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 109 2001-11-20 preliminary figure 37 motorola read cycle figure 38 motorola write cycle address data t rd t df t ri t t rr t rwd t dsd t as a0-a4 r/w csxds d0-d7 address data t wd t dw t wi t ww t t rwd t dsd t as a0-a4 r/w csxds d0-d7 pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 110 2001-11-20 preliminary 7.4 jtag interface timing table 27 jtag interface timing parameter symbol limit values unit notes min. typ. max. test clock (tck) period t tcj 100 ns test clock (tck) period low t cjl 40 ns test clock (tck) period high t cjh 40 ns tms set-up time before tck rising edge t suj 5ns tms hold time after tck rising edge t hjr 5ns tdi set-up time before tck rising edge t dse 5ns tdi hold time after tck rising edge t dhe 5ns input data set-up time t ipj 10 ns input data hold time t iaj 10 ns tdo delay after tck falling edge t odf 20 ns any output pin delay after tck falling edge t opd 25 ns in update-dr tap controller state test reset t trst 1s pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 111 2001-11-20 preliminary figure 39 boundary scan timing tck tms tdi td0 t tcj t cjl t cjh t suj t hjr t dse t dhe t odf t opd t ipj t iaj any input any output t trst trst pef 20450 / 20470 / 24470 timing diagrams preliminary data sheet 112 2001-11-20 preliminary 7.5 hardware reset timing figure 40 hardware reset timing table 28 hardware reset timing parameter symbol limit values unit notes min. typ. max. hardware reset time t reset 1s t reset reset switi_090.emf pef 20450 / 20470 / 24470 electrical characteristics preliminary data sheet 113 2001-11-20 preliminary 8 electrical characteristics 8.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 8.2 operating range note: in the operating range, the functions given in the circuit description are fulfilled. table 29 absolute maximum ratings parameter symbol limit values unit ambient temperature under bias pef t a ? 40 to 85 c storage temperature t stg ? 65 to 150 c supply voltage v dd ? 0.5 to 4.6 v voltage on any input or output pin (referenced to ground) v s ? 0.5 to 5.5 v esd robustness 1) (hbm: 1.5 k ? , 100 pf) 1) according to mil-std 883d, method 3015.7 and esd ass. standard eos/esd-5.1-1993. v esd,hbm 1500 v table 30 operating range parameter symbol limit values unit min. max. operating temperature t a ? 40 85 c supply voltage v dd 3.13 3.47 v ground v ss 00v voltage applied to input pins v in 05.5v voltage applied to output or i/o pins outputs enabled outputs high-z v out v out 0 0 v dd 5.5 v v pef 20450 / 20470 / 24470 electrical characteristics preliminary data sheet 114 2001-11-20 preliminary 8.3 crystal oscillator the switi requires a 16.384 mhz or 32.768 mhz clock source. to supply this a 16.384 mhz or 32.768 mhz crystal can be connected between the eclki and eclko pins. figure 41 shows the crystal with the external capacitors. figure 41 external crystal if a crystal is not used, a 16.384 mhz or a 32.768 mhz signal must be provided to the eclki pin and eclko should be left unconnected. table 31 external capacitances for crystal (recommendation) parameter symbol rec. values unit notes clock external input capacitance c eclki 12 pf clock external output capacitance c eclko 18 pf eclki eclko switi_061.emf 16.384 mhz or 32.768 mhz switi pef 20450 / 20470 / 24470 electrical characteristics preliminary data sheet 115 2001-11-20 preliminary 8.4 dc characteristics note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. 8.5 capacitances table 32 dc characteristics parameter symbol limit values unit notes min. max. input low voltage v il ? 0.3 0.8 v input high voltage v ih 2.0 v dd +3.3 v the maximum v ih must not exceed 5.5 v output low voltage v ol 0.4 v i ol =6ma output high voltage v oh 2.4 v i oh = ? 2.0 ma typical power supply current i cc 200 ma v dd =3.3v, t a =25 c: pdc = 16.384 mhz input leakage current i il 1 a v dd =3.3v, gnd=0v; all other pins are floating; v in =0v output leakage current i oz 1 a v dd =3.3v, gnd=0v; v out =0v table 33 input/output capacitances parameter symbol limit values unit notes typ. eclki input capacitance c eclki 7pf f c =1 mhz the pins, which are not under test, are connected to gnd eclko output capacitance c eclko 7pf input capacitance c in 5pf output capacitance c out 5pf pef 20450 / 20470 / 24470 electrical characteristics preliminary data sheet 116 2001-11-20 preliminary 8.6 ac characteristics ambient temperature under bias range, vdd = 3.3 v 5 %. inputs are driven to 2.4 v for a logical ? 1 ? and to 0.4 v for a logical ? 0 ? . timing measurements for all other signals are made at 2.0 v for a logical ? 1 ? and at 0.8 v for a logical ? 0 ? . the ac-testing input/output wave forms are shown below. figure 42 i/o wave form for ac-test test points 2.4 v 0.4 v 2.0 v 0.8 v 2.0 v d evice u nder t est cl = 50 pf pcm 150 pf 0.8 v pef 20450 / 20470 / 24470 package outlines preliminary data sheet 117 2001-11-20 preliminary 9 package outlines figure 43 outlines of p-mqfp-100-2 p-mqfp-100-2 (plastic metric quad flat package) gpr05365.eps sorts of packing package outlines for tubes, trays etc. are contained in our data book ? package information ? . dimensions in mm smd = surface mounted device pef 20450 / 20470 / 24470 preliminary data sheet 118 2001-11-20 preliminary a analyze memory 20 b bidirectional switching 18 boundary scan 35, 37 broadcast 7 broadcast switching 18 c clock shift 6 constant delay 6, 17 d data rate adaption 6 f flexible data rates 6 frame group 34 framing group 7 g general purpose clocks 7, 33 gpio port 7, 33 i initialization procedure 82 input/output tolerance 8 interrupts masking 75 l local bus interface 12, 29 m message mode 7 microprocessor interface 7, 13, 16, 31 minimum delay 6 multipoint 7 multipoint switching 17 p parallel mode 6, 19, 104 pef 20450 / 20470 / 24470 preliminary data sheet 119 2001-11-20 preliminary r read access 7 register configuration command register 1 49 configuration command register 2 52 configuration register 66 connection command register 47, 69 destination address register 68 destination port address register 42 general input register 69 general input register 1 44 general input register 2 46 general purpose direction register 61 general purpose interrupt register 62 general purpose mask register 62 general purpose port input register 61 general purpose port output register 61 idcode register 71 input time slot address register 42 interrupt error mask register 1 60 interrupt error mask register 2 60 interrupt error status register 70 interrupt error status register 1 58 interrupt error status register 2 58 interrupt mask register 1 59 interrupt status register 1 57 message value register 56 output time slot address register 43 source address register 68 source port address register 42 sub-channel address register 43 time-slot value / configuration register 71 time-slot value register 63 s subchannel switching 6, 90 w write access 7 http://www.infineon.com published by infineon technologies ag infineon goes for business excellence ? business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction. ? dr. ulrich schumacher |
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